Datasheet Texas Instruments CDC2510 — Datenblatt

HerstellerTexas Instruments
SerieCDC2510
Datasheet Texas Instruments CDC2510

3,3-V-Phasenregelkreis-Treiber

Datenblätter

CDC2510: 3.3-V Phase-Lock Loop Clock Driver datasheet
PDF, 608 Kb, Revision: B, Datei veröffentlicht: Dec 2, 2004
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Preise

Status

CDC2510PWRCDC2510PWRG4
Lifecycle StatusNRND (Not recommended for new designs)NRND (Not recommended for new designs)
Manufacture's Sample AvailabilityNoNo

Verpackung

CDC2510PWRCDC2510PWRG4
N12
Pin2424
Package TypePWPW
Industry STD TermTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-G
Package QTY20002000
CarrierLARGE T&RLARGE T&R
Device MarkingCK2510CK2510
Width (mm)4.44.4
Length (mm)7.87.8
Thickness (mm)11
Pitch (mm).65.65
Max Height (mm)1.21.2
Mechanical DataHerunterladenHerunterladen

Öko-Plan

CDC2510PWRCDC2510PWRG4
RoHSCompliantCompliant

Anwendungshinweise

  • Understanding the Differences Between CDC2509x/10x Devices
    PDF, 65 Kb, Datei veröffentlicht: Jan 8, 1999
    This application note provides information concerning the various revisions of the TI CDC2509/10 family of devices. In addition, it will assist designers with new and existing designs. Phase error information, both slope and absolute value, is provided to assist in the tuning process. Furthermore, a table summarizes important parameters for choosing the correct PLL. The table contains capacitance
  • High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)
    PDF, 109 Kb, Revision: A, Datei veröffentlicht: Sep 23, 1998
    The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo

Modellreihe

Serie: CDC2510 (2)

Herstellerklassifikation

  • Semiconductors> Clock and Timing> Clock Buffers> Zero Delay Buffers