Datasheet Texas Instruments CDC2510PWRG4 — Datenblatt
| Hersteller | Texas Instruments |
| Serie | CDC2510 |
| Artikelnummer | CDC2510PWRG4 |
3,3-V-Phasenregelkreistakttreiber 24-TSSOP
Datenblätter
CDC2510: 3.3-V Phase-Lock Loop Clock Driver datasheet
PDF, 608 Kb, Revision: B, Datei veröffentlicht: Dec 2, 2004
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Preise
Status
| Lifecycle Status | NRND (Not recommended for new designs) |
| Manufacture's Sample Availability | No |
Verpackung
| Pin | 24 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | CK2510 |
| Width (mm) | 4.4 |
| Length (mm) | 7.8 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Herunterladen |
Öko-Plan
| RoHS | Compliant |
Anwendungshinweise
- Understanding the Differences Between CDC2509x/10x DevicesPDF, 65 Kb, Datei veröffentlicht: Jan 8, 1999
This application note provides information concerning the various revisions of the TI CDC2509/10 family of devices. In addition, it will assist designers with new and existing designs. Phase error information, both slope and absolute value, is provided to assist in the tuning process. Furthermore, a table summarizes important parameters for choosing the correct PLL. The table contains capacitance - High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)PDF, 109 Kb, Revision: A, Datei veröffentlicht: Sep 23, 1998
The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo
Modellreihe
Serie: CDC2510 (2)
- CDC2510PWR CDC2510PWRG4
Herstellerklassifikation
- Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers