Datasheet Texas Instruments CDC2509A — Datenblatt

HerstellerTexas Instruments
SerieCDC2509A
Datasheet Texas Instruments CDC2509A

3,3-V-Phasenregelkreistakttreiber mit 3-Zustands-Ausgängen

Datenblätter

CDC2509A: 3.3 V Phase Lock Loop Clock Driver (Rev. C)
PDF, 614 Kb, Revision: C, Datei veröffentlicht: Dec 2, 2004

Preise

Status

CDC2509APWRCDC2509APWRG4
Lifecycle StatusNRND (Not recommended for new designs)NRND (Not recommended for new designs)
Manufacture's Sample AvailabilityNoNo

Verpackung

CDC2509APWRCDC2509APWRG4
N12
Pin2424
Package TypePWPW
Industry STD TermTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-G
Package QTY20002000
CarrierLARGE T&RLARGE T&R
Device MarkingCK2509ACK2509A
Width (mm)4.44.4
Length (mm)7.87.8
Thickness (mm)11
Pitch (mm).65.65
Max Height (mm)1.21.2
Mechanical DataHerunterladenHerunterladen

Öko-Plan

CDC2509APWRCDC2509APWRG4
RoHSCompliantCompliant
Pb FreeYesYes

Anwendungshinweise

  • Using CDC2509A/CDC2510A PLL With Spread Spectrum Clocking (SSC)
    PDF, 454 Kb, Datei veröffentlicht: Jan 5, 1999
    This application note describes the CDC2509A/2510A [1] phase-lock loop clockdrivers and their use with spread spectrum clocking system. This application note gives SSC system performance measurements and parameter measurementinstructions.
  • High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)
    PDF, 109 Kb, Revision: A, Datei veröffentlicht: Sep 23, 1998
    The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo

Modellreihe

Serie: CDC2509A (2)

Herstellerklassifikation

  • Semiconductors> Clock and Timing> Clock Buffers> Zero Delay Buffers