Datasheet Texas Instruments CDC2509PWR — Datenblatt

3,3-V-Phasenregelkreistakttreiber mit 3-Zustands-Ausgängen 24-TSSOP

Datenblätter

PDF, 614 Kb, Revision: C, Datei veröffentlicht: Dec 2, 2004

Lifecycle Status	NRND (Not recommended for new designs)
Manufacture's Sample Availability	No

RoHS	Compliant
Pb Free	Yes

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Understanding the Differences Between CDC2509x/10x Devices
PDF, 65 Kb, Datei veröffentlicht: Jan 8, 1999
This application note provides information concerning the various revisions of the TI CDC2509/10 family of devices. In addition, it will assist designers with new and existing designs. Phase error information, both slope and absolute value, is provided to assist in the tuning process. Furthermore, a table summarizes important parameters for choosing the correct PLL. The table contains capacitance
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High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)
PDF, 109 Kb, Revision: A, Datei veröffentlicht: Sep 23, 1998
The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo

Serie: CDC2509 (2)