Datasheet Texas Instruments CD74HCT109 — Datenblatt
| Hersteller | Texas Instruments |
| Serie | CD74HCT109 |
Hochgeschwindigkeits-CMOS-Logik-Dual-Positive-Edge-Triggered JK-Flipflops mit Set und Reset
Datenblätter
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 datasheet
PDF, 458 Kb, Revision: E, Datei veröffentlicht: Oct 13, 2003
Auszug aus dem Dokument
Preise
Status
| CD74HCT109E | CD74HCT109EE4 | CD74HCT109M | CD74HCT109M96 | CD74HCT109MG4 | |
|---|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No | No | No | No |
Verpackung
| CD74HCT109E | CD74HCT109EE4 | CD74HCT109M | CD74HCT109M96 | CD74HCT109MG4 | |
|---|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 | 5 |
| Pin | 16 | 16 | 16 | 16 | 16 |
| Package Type | N | N | D | D | D |
| Industry STD Term | PDIP | PDIP | SOIC | SOIC | SOIC |
| JEDEC Code | R-PDIP-T | R-PDIP-T | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 25 | 25 | 40 | 2500 | 40 |
| Carrier | TUBE | TUBE | TUBE | LARGE T&R | TUBE |
| Device Marking | CD74HCT109E | CD74HCT109E | HCT109M | HCT109M | HCT109M |
| Width (mm) | 6.35 | 6.35 | 3.91 | 3.91 | 3.91 |
| Length (mm) | 19.3 | 19.3 | 9.9 | 9.9 | 9.9 |
| Thickness (mm) | 3.9 | 3.9 | 1.58 | 1.58 | 1.58 |
| Pitch (mm) | 2.54 | 2.54 | 1.27 | 1.27 | 1.27 |
| Max Height (mm) | 5.08 | 5.08 | 1.75 | 1.75 | 1.75 |
| Mechanical Data | Herunterladen | Herunterladen | Herunterladen | Herunterladen | Herunterladen |
Parameter
| Parameters / Models | CD74HCT109E | CD74HCT109EE4 | CD74HCT109M | CD74HCT109M96 | CD74HCT109MG4 |
|---|---|---|---|---|---|
| Bits | 2 | 2 | 2 | 2 | 2 |
| F @ Nom Voltage(Max), Mhz | 25 | 25 | 25 | 25 | 25 |
| ICC @ Nom Voltage(Max), mA | 0.04 | 0.04 | 0.04 | 0.04 | 0.04 |
| Output Drive (IOL/IOH)(Max), mA | -6/6 | -6/6 | -6/6 | -6/6 | -6/6 |
| Package Group | PDIP | PDIP | SOIC | SOIC | SOIC |
| Package Size: mm2:W x L, PKG | See datasheet (PDIP) | See datasheet (PDIP) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) |
| Rating | Catalog | Catalog | Catalog | Catalog | Catalog |
| Schmitt Trigger | No | No | No | No | No |
| Technology Family | HCT | HCT | HCT | HCT | HCT |
| VCC(Max), V | 5.5 | 5.5 | 5.5 | 5.5 | 5.5 |
| VCC(Min), V | 4.5 | 4.5 | 4.5 | 4.5 | 4.5 |
| Voltage(Nom), V | 5 | 5 | 5 | 5 | 5 |
| tpd @ Nom Voltage(Max), ns | 50 | 50 | 50 | 50 | 50 |
Öko-Plan
| CD74HCT109E | CD74HCT109EE4 | CD74HCT109M | CD74HCT109M96 | CD74HCT109MG4 | |
|---|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant | Compliant |
| Pb Free | Yes | Yes |
Anwendungshinweise
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015
Modellreihe
Serie: CD74HCT109 (5)
Herstellerklassifikation
- Semiconductors> Logic> Flip-Flop/Latch/Register> J-K Flip-Flop