Datasheet Texas Instruments CD74HCT107 — Datenblatt

HerstellerTexas Instruments
SerieCD74HCT107
Datasheet Texas Instruments CD74HCT107

Hochgeschwindigkeits-CMOS-Logik-Dual-Negative-Edge-Triggered JK-Flip-Flops mit Reset

Datenblätter

CD54HC107, CD74HC107, CD54HCT107, CD74HCT107 datasheet
PDF, 722 Kb, Revision: D, Datei veröffentlicht: Oct 21, 2003
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Preise

Status

CD74HCT107ECD74HCT107EE4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNo

Verpackung

CD74HCT107ECD74HCT107EE4
N12
Pin1414
Package TypeNN
Industry STD TermPDIPPDIP
JEDEC CodeR-PDIP-TR-PDIP-T
Package QTY2525
CarrierTUBETUBE
Device MarkingCD74HCT107ECD74HCT107E
Width (mm)6.356.35
Length (mm)19.319.3
Thickness (mm)3.93.9
Pitch (mm)2.542.54
Max Height (mm)5.085.08
Mechanical DataHerunterladenHerunterladen

Parameter

Parameters / ModelsCD74HCT107E
CD74HCT107E
CD74HCT107EE4
CD74HCT107EE4
Bits22
F @ Nom Voltage(Max), Mhz2525
ICC @ Nom Voltage(Max), mA0.040.04
Output Drive (IOL/IOH)(Max), mA-6/6-6/6
Package GroupPDIPPDIP
Package Size: mm2:W x L, PKGSee datasheet (PDIP)See datasheet (PDIP)
RatingCatalogCatalog
Schmitt TriggerNoNo
Technology FamilyHCTHCT
VCC(Max), V5.55.5
VCC(Min), V4.54.5
Voltage(Nom), V55
tpd @ Nom Voltage(Max), ns4343

Öko-Plan

CD74HCT107ECD74HCT107EE4
RoHSCompliantCompliant
Pb FreeYesYes

Anwendungshinweise

  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015

Modellreihe

Serie: CD74HCT107 (2)

Herstellerklassifikation

  • Semiconductors> Logic> Flip-Flop/Latch/Register> J-K Flip-Flop