Datasheet Texas Instruments CD74HC112MT — Datenblatt

Hersteller	Texas Instruments
Serie	CD74HC112
Artikelnummer	CD74HC112MT

Hochgeschwindigkeits-CMOS-Logik-Dual-Negative-Edge-Triggered JK-Flip-Flops mit 16-SOIC -55 auf 125 setzen und zurücksetzen

Datenblätter

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PDF, 749 Kb, Revision: H, Datei veröffentlicht: Oct 13, 2003

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Preise

Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Verpackung

Pin	16
Package Type	D
Industry STD Term	SOIC
JEDEC Code	R-PDSO-G
Package QTY	250
Carrier	SMALL T&R
Device Marking	HC112M
Width (mm)	3.91
Length (mm)	9.9
Thickness (mm)	1.58
Pitch (mm)	1.27
Max Height (mm)	1.75
Mechanical Data	Herunterladen

Parameter

Bits	2
F @ Nom Voltage(Max)	70 Mhz
ICC @ Nom Voltage(Max)	0.04 mA
Output Drive (IOL/IOH)(Max)	-6/6 mA
Package Group	SOIC
Package Size: mm2:W x L	16SOIC: 59 mm2: 6 x 9.9(SOIC) PKG
Rating	Catalog
Schmitt Trigger	No
Technology Family	HC
VCC(Max)	6 V
VCC(Min)	2 V
Voltage(Nom)	3.3,5 V
tpd @ Nom Voltage(Max)	53 ns

Öko-Plan

RoHS

Compliant

Anwendungshinweise

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Modellreihe

Serie: CD74HC112 (9)

CD74HC112E CD74HC112M96 CD74HC112MT CD74HC112NSR CD74HC112PW CD74HC112PWR CD74HC112PWRE4 CD74HC112PWRG4 CD74HC112PWT

Herstellerklassifikation

Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop