Datasheet Texas Instruments CD74AC573 — Datenblatt

Hersteller	Texas Instruments
Serie	CD74AC573

Oktale transparente nicht invertierende Latches mit 3-Zustands-Ausgängen

Datenblätter

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PDF, 1.3 Mb, Datei veröffentlicht: Dec 3, 1998

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Data sheet acquired from Harris Semiconductor
SCHS291 This data sheet is applicable to the CD74AC563, CD54/74AC573, and CD54/74ACT573. The CD54AC563 and CD54/74ACT563 were
not acquired from Harris Semiconductor. PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION
Orderable Device Status
(1) Package Type Package Pins Package
Drawing
Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (В°C) Device Marking
(4/5) CD54AC573F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 CD54AC573F3A CD54ACT573F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 CD54ACT573F3A CD74AC573E ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74AC573E CD74AC573M ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC573M CD74AC573M96 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC573M CD74AC573M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC573M CD74AC573M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC573M CD74AC573MG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC573M CD74ACT573E ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74ACT573E CD74ACT573EE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74ACT573E CD74ACT573M ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT573M CD74ACT573M96 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT573M CD74ACT573MG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT573M (1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available. …

Preise

Status

	CD74AC573E	CD74AC573M	CD74AC573M96	CD74AC573M96E4	CD74AC573M96G4	CD74AC573MG4
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	No	No	No	No

Verpackung

	CD74AC573E	CD74AC573M	CD74AC573M96	CD74AC573M96E4	CD74AC573M96G4	CD74AC573MG4
N	1	2	3	4	5	6
Pin	20	20	20	20	20	20
Package Type	N	DW	DW	DW	DW	DW
Industry STD Term	PDIP	SOIC	SOIC	SOIC	SOIC	SOIC
JEDEC Code	R-PDIP-T	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	20	25	2000	2000	2000	25
Carrier	TUBE	TUBE	LARGE T&R	LARGE T&R	LARGE T&R	TUBE
Device Marking	CD74AC573E	AC573M	AC573M	AC573M	AC573M	AC573M
Width (mm)	6.35	7.5	7.5	7.5	7.5	7.5
Length (mm)	24.33	12.8	12.8	12.8	12.8	12.8
Thickness (mm)	4.57	2.35	2.35	2.35	2.35	2.35
Pitch (mm)	2.54	1.27	1.27	1.27	1.27	1.27
Max Height (mm)	5.08	2.65	2.65	2.65	2.65	2.65
Mechanical Data	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen

Parameter

Parameters / Models	CD74AC573E	CD74AC573M	CD74AC573M96	CD74AC573M96E4	CD74AC573M96G4	CD74AC573MG4
3-State Output	Yes	Yes	Yes	Yes	Yes	Yes
Bits	8	8	8	8	8	8
F @ Nom Voltage(Max), Mhz	100	100	100	100	100	100
ICC @ Nom Voltage(Max), mA	0.08	0.08	0.08	0.08	0.08	0.08
Operating Temperature Range, C	-55 to 125	-55 to 125	-55 to 125	-55 to 125	-55 to 125	-55 to 125
Output Drive (IOL/IOH)(Max), mA	24/-24	24/-24	24/-24	24/-24	24/-24	24/-24
Package Group	PDIP	SOIC	SOIC	SOIC	SOIC	SOIC
Package Size: mm2:W x L, PKG	See datasheet (PDIP)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No	No	No
Technology Family	AC	AC	AC	AC	AC	AC
VCC(Max), V	5.5	5.5	5.5	5.5	5.5	5.5
VCC(Min), V	1.5	1.5	1.5	1.5	1.5	1.5
Voltage(Nom), V	1.5,3.3,5	1.5,3.3,5	1.5,3.3,5	1.5,3.3,5	1.5,3.3,5	1.5,3.3,5
tpd @ Nom Voltage(Max), ns	119,13.4,9.5	119,13.4,9.5	119,13.4,9.5	119,13.4,9.5	119,13.4,9.5	119,13.4,9.5

Öko-Plan

	CD74AC573E	CD74AC573M	CD74AC573M96	CD74AC573M96E4	CD74AC573M96G4	CD74AC573MG4
RoHS	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant
Pb Free	Yes

Anwendungshinweise

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Power-Up Behavior of Clocked Devices (Rev. A)
PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015
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Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
PDF, 43 Kb, Datei veröffentlicht: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Modellreihe

Serie: CD74AC573 (6)

CD74AC573E CD74AC573M CD74AC573M96 CD74AC573M96E4 CD74AC573M96G4 CD74AC573MG4

Herstellerklassifikation

Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Latch