Datasheet Texas Instruments CD74AC373 — Datenblatt
Hersteller | Texas Instruments |
Serie | CD74AC373 |
Oktale transparente Latches mit 3-Zustands-Ausgängen
Datenblätter
Octal Transparent Latch, 3-State datasheet
PDF, 1.3 Mb, Datei veröffentlicht: Dec 3, 1998
Auszug aus dem Dokument
Preise
Status
CD74AC373E | CD74AC373M | CD74AC373M96 | CD74AC373MG4 | |
---|---|---|---|---|
Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
Manufacture's Sample Availability | No | No | No | No |
Verpackung
CD74AC373E | CD74AC373M | CD74AC373M96 | CD74AC373MG4 | |
---|---|---|---|---|
N | 1 | 2 | 3 | 4 |
Pin | 20 | 20 | 20 | 20 |
Package Type | N | DW | DW | DW |
Industry STD Term | PDIP | SOIC | SOIC | SOIC |
JEDEC Code | R-PDIP-T | R-PDSO-G | R-PDSO-G | R-PDSO-G |
Package QTY | 20 | 25 | 2000 | 25 |
Carrier | TUBE | TUBE | LARGE T&R | TUBE |
Device Marking | CD74AC373E | AC373M | AC373M | AC373M |
Width (mm) | 6.35 | 7.5 | 7.5 | 7.5 |
Length (mm) | 24.33 | 12.8 | 12.8 | 12.8 |
Thickness (mm) | 4.57 | 2.35 | 2.35 | 2.35 |
Pitch (mm) | 2.54 | 1.27 | 1.27 | 1.27 |
Max Height (mm) | 5.08 | 2.65 | 2.65 | 2.65 |
Mechanical Data | Herunterladen | Herunterladen | Herunterladen | Herunterladen |
Parameter
Parameters / Models | CD74AC373E | CD74AC373M | CD74AC373M96 | CD74AC373MG4 |
---|---|---|---|---|
3-State Output | Yes | Yes | Yes | Yes |
Bits | 8 | 8 | 8 | 8 |
F @ Nom Voltage(Max), Mhz | 100 | 100 | 100 | 100 |
ICC @ Nom Voltage(Max), mA | 0.08 | 0.08 | 0.08 | 0.08 |
Operating Temperature Range, C | -55 to 125 | -55 to 125 | -55 to 125 | -55 to 125 |
Output Drive (IOL/IOH)(Max), mA | 24/-24 | 24/-24 | 24/-24 | 24/-24 |
Package Group | PDIP | SOIC | SOIC | SOIC |
Package Size: mm2:W x L, PKG | See datasheet (PDIP) | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) |
Rating | Catalog | Catalog | Catalog | Catalog |
Schmitt Trigger | No | No | No | No |
Technology Family | AC | AC | AC | AC |
VCC(Max), V | 5.5 | 5.5 | 5.5 | 5.5 |
VCC(Min), V | 1.5 | 1.5 | 1.5 | 1.5 |
Voltage(Nom), V | 1.5,3.3,5 | 1.5,3.3,5 | 1.5,3.3,5 | 1.5,3.3,5 |
tpd @ Nom Voltage(Max), ns | 96,10.8,7.7 | 96,10.8,7.7 | 96,10.8,7.7 | 96,10.8,7.7 |
Öko-Plan
CD74AC373E | CD74AC373M | CD74AC373M96 | CD74AC373MG4 | |
---|---|---|---|---|
RoHS | Compliant | Compliant | Compliant | Compliant |
Pb Free | Yes |
Anwendungshinweise
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, Datei veröffentlicht: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
Modellreihe
Serie: CD74AC373 (4)
Herstellerklassifikation
- Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Latch