Datasheet Texas Instruments CD74AC112 — Datenblatt

HerstellerTexas Instruments
SerieCD74AC112
Datasheet Texas Instruments CD74AC112

Dual Negative-Edge-Triggered JK Flip-Flops mit Set und Reset

Datenblätter

CD54AC112, CD74AC112 datasheet
PDF, 857 Kb, Datei veröffentlicht: Jan 17, 2003
Auszug aus dem Dokument

Preise

Status

CD74AC112ECD74AC112EE4CD74AC112MCD74AC112M96CD74AC112M96G4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNo

Verpackung

CD74AC112ECD74AC112EE4CD74AC112MCD74AC112M96CD74AC112M96G4
N12345
Pin1616161616
Package TypeNNDDD
Industry STD TermPDIPPDIPSOICSOICSOIC
JEDEC CodeR-PDIP-TR-PDIP-TR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY2525402500
CarrierTUBETUBETUBELARGE T&R
Device MarkingCD74AC112ECD74AC112EAC112MAC112M
Width (mm)6.356.353.913.913.91
Length (mm)19.319.39.99.99.9
Thickness (mm)3.93.91.581.581.58
Pitch (mm)2.542.541.271.271.27
Max Height (mm)5.085.081.751.751.75
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Parameter

Parameters / ModelsCD74AC112E
CD74AC112E
CD74AC112EE4
CD74AC112EE4
CD74AC112M
CD74AC112M
CD74AC112M96
CD74AC112M96
CD74AC112M96G4
CD74AC112M96G4
Approx. Price (US$)0.19 | 1ku
Bits2222
Bits(#)2
F @ Nom Voltage(Max), Mhz100100100100
F @ Nom Voltage(Max)(Mhz)100
ICC @ Nom Voltage(Max), mA0.040.040.040.04
ICC @ Nom Voltage(Max)(mA)0.04
Output Drive (IOL/IOH)(Max), mA-24/24-24/24-24/24-24/24
Output Drive (IOL/IOH)(Max)(mA)-24/24
Package GroupPDIPPDIPSOICSOICSOIC
Package Size: mm2:W x L, PKGSee datasheet (PDIP)See datasheet (PDIP)16SOIC: 59 mm2: 6 x 9.9(SOIC)16SOIC: 59 mm2: 6 x 9.9(SOIC)
Package Size: mm2:W x L (PKG)See datasheet (PDIP)
RatingCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNo
Technology FamilyACACACACAC
VCC(Max), V5.55.55.55.5
VCC(Max)(V)5.5
VCC(Min), V1.51.51.51.5
VCC(Min)(V)1.5
Voltage(Nom), V3.3,53.3,53.3,53.3,5
Voltage(Nom)(V)3.3
5
tpd @ Nom Voltage(Max), ns11.111.111.111.1
tpd @ Nom Voltage(Max)(ns)11.1

Öko-Plan

CD74AC112ECD74AC112EE4CD74AC112MCD74AC112M96CD74AC112M96G4
RoHSCompliantCompliantCompliantCompliantNot Compliant
Pb FreeNoYesYes

Anwendungshinweise

  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, Datei veröffentlicht: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Flip-Flop/Latch/Register> J-K Flip-Flop