Datasheet Texas Instruments CD74AC112E — Datenblatt

HerstellerTexas Instruments
SerieCD74AC112
ArtikelnummerCD74AC112E
Datasheet Texas Instruments CD74AC112E

Dual Negative-Edge-Triggered JK Flip-Flops mit Set und Reset 16-PDIP -55 auf 125

Datenblätter

CD54AC112, CD74AC112 datasheet
PDF, 857 Kb, Datei veröffentlicht: Jan 17, 2003
Auszug aus dem Dokument

Preise

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Verpackung

Pin16
Package TypeN
Industry STD TermPDIP
JEDEC CodeR-PDIP-T
Package QTY25
CarrierTUBE
Device MarkingCD74AC112E
Width (mm)6.35
Length (mm)19.3
Thickness (mm)3.9
Pitch (mm)2.54
Max Height (mm)5.08
Mechanical DataHerunterladen

Parameter

Bits2
F @ Nom Voltage(Max)100 Mhz
ICC @ Nom Voltage(Max)0.04 mA
Output Drive (IOL/IOH)(Max)-24/24 mA
Package GroupPDIP
Package Size: mm2:W x LSee datasheet (PDIP) PKG
RatingCatalog
Schmitt TriggerNo
Technology FamilyAC
VCC(Max)5.5 V
VCC(Min)1.5 V
Voltage(Nom)3.3,5 V
tpd @ Nom Voltage(Max)11.1 ns

Öko-Plan

RoHSCompliant
Pb FreeYes

Anwendungshinweise

  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, Datei veröffentlicht: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Modellreihe

Herstellerklassifikation

  • Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop