Datasheet Texas Instruments CD74AC112M — Datenblatt
| Hersteller | Texas Instruments |
| Serie | CD74AC112 |
| Artikelnummer | CD74AC112M |
Dual Negative-Edge-Triggered JK Flip-Flops mit Set und Reset 16-SOIC -55 auf 125
Datenblätter
CD54AC112, CD74AC112 datasheet
PDF, 857 Kb, Datei veröffentlicht: Jan 17, 2003
Auszug aus dem Dokument
Preise
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Verpackung
| Pin | 16 |
| Package Type | D |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 40 |
| Carrier | TUBE |
| Device Marking | AC112M |
| Width (mm) | 3.91 |
| Length (mm) | 9.9 |
| Thickness (mm) | 1.58 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 1.75 |
| Mechanical Data | Herunterladen |
Parameter
| Bits | 2 |
| F @ Nom Voltage(Max) | 100 Mhz |
| ICC @ Nom Voltage(Max) | 0.04 mA |
| Output Drive (IOL/IOH)(Max) | -24/24 mA |
| Package Group | SOIC |
| Package Size: mm2:W x L | 16SOIC: 59 mm2: 6 x 9.9(SOIC) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | AC |
| VCC(Max) | 5.5 V |
| VCC(Min) | 1.5 V |
| Voltage(Nom) | 3.3,5 V |
| tpd @ Nom Voltage(Max) | 11.1 ns |
Öko-Plan
| RoHS | Compliant |
Anwendungshinweise
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, Datei veröffentlicht: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
Modellreihe
Serie: CD74AC112 (5)
- CD74AC112E CD74AC112EE4 CD74AC112M CD74AC112M96 CD74AC112M96G4
Herstellerklassifikation
- Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop