Datasheet Texas Instruments CD54HCT112 — Datenblatt

HerstellerTexas Instruments
SerieCD54HCT112
Datasheet Texas Instruments CD54HCT112

Hochgeschwindigkeits-CMOS-Logik-Dual-JK-Flip-Flops mit Set- und Reset-Trigger mit negativer Flanke

Datenblätter

CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 datasheet
PDF, 749 Kb, Revision: H, Datei veröffentlicht: Oct 13, 2003
Auszug aus dem Dokument

Preise

Status

5962-8970201EACD54HCT112F3A
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNo

Verpackung

5962-8970201EACD54HCT112F3A
N12
Pin1616
Package TypeJJ
Industry STD TermCDIPCDIP
JEDEC CodeR-GDIP-TR-GDIP-T
Package QTY11
CarrierTUBETUBE
Width (mm)6.926.92
Length (mm)19.5619.56
Thickness (mm)4.574.57
Pitch (mm)2.542.54
Max Height (mm)5.085.08
Mechanical DataHerunterladenHerunterladen
Device Marking5962-8970201EA

Parameter

Parameters / Models5962-8970201EA
5962-8970201EA
CD54HCT112F3A
CD54HCT112F3A
Bits22
F @ Nom Voltage(Max), Mhz2525
ICC @ Nom Voltage(Max), mA0.040.04
Input TypeTTLTTL
Operating Temperature Range, C-55 to 125-55 to 125
Output Drive (IOL/IOH)(Max), mA-6/6-6/6
Output TypeCMOSCMOS
Package GroupCDIPCDIP
Package Size: mm2:W x L, PKGSee datasheet (CDIP)See datasheet (CDIP)
RatingMilitaryMilitary
Technology FamilyHCTHCT
VCC(Max), V5.55.5
VCC(Min), V4.54.5
tpd @ Nom Voltage(Max), ns4444

Öko-Plan

5962-8970201EACD54HCT112F3A
RoHSSee ti.comSee ti.com

Anwendungshinweise

  • SN54/74HCT CMOS Logic Family Applications and Restrictions
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    The TI SN54/74HCT family of CMOS devices is a subgroup of the SN74HC series with the HCT circuitry modified to meet the interfacing requirements of TTL outputs to high-speed CMOS inputs. The HCT devices can be driven by the TTL circuits directly without additional components. This document describes the TTL/HC interface the operating voltages circuit noise and power consumption. A Bergeron anal
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    The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con
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    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • Designing With Logic (Rev. C)
    PDF, 186 Kb, Revision: C, Datei veröffentlicht: Jun 1, 1997
    Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w
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    PDF, 93 Kb, Datei veröffentlicht: Apr 30, 2015
  • Implications of Slow or Floating CMOS Inputs (Rev. D)
    PDF, 260 Kb, Revision: D, Datei veröffentlicht: Jun 23, 2016
  • CMOS Power Consumption and CPD Calculation (Rev. B)
    PDF, 89 Kb, Revision: B, Datei veröffentlicht: Jun 1, 1997
    Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, Datei veröffentlicht: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Modellreihe

Serie: CD54HCT112 (2)

Herstellerklassifikation

  • Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers