Datasheet Texas Instruments CD54ACT109 — Datenblatt
Hersteller | Texas Instruments |
Serie | CD54ACT109 |
Dual Positive-Edge Triggered JK Flip-Flops mit Set und Reset
Datenblätter
CD54ACT109, CD74ACT109 datasheet
PDF, 878 Kb, Datei veröffentlicht: Jan 24, 2003
Auszug aus dem Dokument
Preise
Status
CD54ACT109F3A | |
---|---|
Lifecycle Status | Active (Recommended for new designs) |
Manufacture's Sample Availability | No |
Verpackung
CD54ACT109F3A | |
---|---|
N | 1 |
Pin | 16 |
Package Type | J |
Industry STD Term | CDIP |
JEDEC Code | R-GDIP-T |
Package QTY | 1 |
Carrier | TUBE |
Device Marking | CD54ACT109F3A |
Width (mm) | 6.92 |
Length (mm) | 19.56 |
Thickness (mm) | 4.57 |
Pitch (mm) | 2.54 |
Max Height (mm) | 5.08 |
Mechanical Data | Herunterladen |
Parameter
Parameters / Models | CD54ACT109F3A |
---|---|
Bits | 2 |
F @ Nom Voltage(Max), Mhz | 90 |
ICC @ Nom Voltage(Max), mA | 0.04 |
Input Type | TTL |
Operating Temperature Range, C | -55 to 125 |
Output Drive (IOL/IOH)(Max), mA | -24/24 |
Output Type | CMOS |
Package Group | CDIP |
Package Size: mm2:W x L, PKG | See datasheet (CDIP) |
Rating | Military |
Technology Family | ACT |
VCC(Max), V | 5.5 |
VCC(Min), V | 4.5 |
tpd @ Nom Voltage(Max), ns | 11.1 |
Öko-Plan
CD54ACT109F3A | |
---|---|
RoHS | See ti.com |
Anwendungshinweise
- Selecting the Right Level Translation Solution (Rev. A)PDF, 313 Kb, Revision: A, Datei veröffentlicht: Jun 22, 2004
Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati - Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, Datei veröffentlicht: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
Modellreihe
Serie: CD54ACT109 (1)
Herstellerklassifikation
- Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers