Datasheet Texas Instruments CD4071B — Datenblatt

HerstellerTexas Instruments
SerieCD4071B
Datasheet Texas Instruments CD4071B

CMOS Quad 2-Input OR Gate

Datenblätter

CD4071B, CD4072B, CD4075B TYPES datasheet
PDF, 1.7 Mb, Revision: D, Datei veröffentlicht: Aug 21, 2003
Auszug aus dem Dokument

Preise

Status

CD4071BECD4071BEE4CD4071BF3AS2534CD4071BMCD4071BM96CD4071BM96G4CD4071BMG4CD4071BMTCD4071BNSRCD4071BNSRG4CD4071BPWCD4071BPWE4CD4071BPWRCD4071BPWRE4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoYesNoNoNoYesNoNoYesNoNo

Verpackung

CD4071BECD4071BEE4CD4071BF3AS2534CD4071BMCD4071BM96CD4071BM96G4CD4071BMG4CD4071BMTCD4071BNSRCD4071BNSRG4CD4071BPWCD4071BPWE4CD4071BPWRCD4071BPWRE4
N1234567891011121314
Pin1414141414141414141414141414
Package TypeNNJDDDDDNSNSPWPWPWPW
Industry STD TermPDIPPDIPCDIPSOICSOICSOICSOICSOICSOPSOPTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDIP-TR-PDIP-TR-GDIP-TR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY252550250025005025020002000909020002000
CarrierTUBETUBETUBELARGE T&RLARGE T&RTUBESMALL T&RLARGE T&RLARGE T&RTUBETUBELARGE T&RLARGE T&R
Device MarkingCD4071BECD4071BECD4071BMCD4071BMCD4071BMCD4071BMCD4071BMCD4071BCD4071BCM071BCM071BCM071BCM071B
Width (mm)6.356.356.673.913.913.913.913.915.35.34.44.44.44.4
Length (mm)19.319.319.568.658.658.658.658.6510.310.35555
Thickness (mm)3.93.94.571.581.581.581.581.581.951.951111
Pitch (mm)2.542.542.541.271.271.271.271.271.271.270.650.650.650.65
Max Height (mm)5.085.085.081.751.751.751.751.75221.21.21.21.2
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen

Parameter

Parameters / ModelsCD4071BE
CD4071BE
CD4071BEE4
CD4071BEE4
CD4071BF3AS2534
CD4071BF3AS2534
CD4071BM
CD4071BM
CD4071BM96
CD4071BM96
CD4071BM96G4
CD4071BM96G4
CD4071BMG4
CD4071BMG4
CD4071BMT
CD4071BMT
CD4071BNSR
CD4071BNSR
CD4071BNSRG4
CD4071BNSRG4
CD4071BPW
CD4071BPW
CD4071BPWE4
CD4071BPWE4
CD4071BPWR
CD4071BPWR
CD4071BPWRE4
CD4071BPWRE4
Approx. Price (US$)0.11 | 1ku
Bits4444444444444
Bits(#)4
F @ Nom Voltage(Max), Mhz8888888888888
F @ Nom Voltage(Max)(Mhz)8
ICC @ Nom Voltage(Max), mA0.0150.0150.0150.0150.0150.0150.0150.0150.0150.0150.0150.0150.015
ICC @ Nom Voltage(Max)(mA)0.015
IOH(Max), mA-1.5-1.5-1.5-1.5-1.5-1.5-1.5-1.5-1.5-1.5-1.5-1.5-1.5
IOL(Max), mA1.51.51.51.51.51.51.51.51.51.51.51.51.5
Input TypeCMOS
Operating Temperature Range, C-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125
Operating Temperature Range(C)-55 to 125
Output Drive (IOL/IOH)(Max)(mA)1.5/-1.5
Output TypeCMOS
Package GroupPDIPPDIPPDIP
SO
SOIC
TSSOP
SOICSOICSOICSOICSOICSOSOTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKGSee datasheet (PDIP)See datasheet (PDIP)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SO: 80 mm2: 7.8 x 10.2(SO)14SO: 80 mm2: 7.8 x 10.2(SO)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)
Package Size: mm2:W x L (PKG)See datasheet (PDIP)
See datasheet (CDIP)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNoNoNoNoNoNoNo
Technology FamilyCD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000
VCC(Max), V18181818181818181818181818
VCC(Max)(V)18
VCC(Min), V3333333333333
VCC(Min)(V)3
Voltage(Nom), V10101010101010101010101010
Voltage(Nom)(V)10
tpd @ Nom Voltage(Max), ns120120120120120120120120120120120120120
tpd @ Nom Voltage(Max)(ns)120

Öko-Plan

CD4071BECD4071BEE4CD4071BF3AS2534CD4071BMCD4071BM96CD4071BM96G4CD4071BMG4CD4071BMTCD4071BNSRCD4071BNSRG4CD4071BPWCD4071BPWE4CD4071BPWRCD4071BPWRE4
RoHSCompliantCompliantNot CompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliant
Pb FreeYesYesNo

Anwendungshinweise

  • Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics
    PDF, 188 Kb, Datei veröffentlicht: Dec 3, 2001
    Both buffered and unbuffered CMOS B-series gates inverters and high-current IC products are available from TI. Each product classification has application advantages in appropriate logic-system designs. Many CMOS suppliers have concentrated on promoting buffered B-series products with applications literature focusing on the attributes and use of the buffered types. This practice has left an imb
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, Datei veröffentlicht: Jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, Revision: C, Datei veröffentlicht: Dec 2, 2015
  • Introduction to Logic
    PDF, 93 Kb, Datei veröffentlicht: Apr 30, 2015

Modellreihe

Herstellerklassifikation

  • Semiconductors > Logic > Gate > OR Gate