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ADS8328

Datasheet Texas Instruments ADS8328 — Datenblatt

HerstellerTexas Instruments
SerieADS8328
Datasheet Texas Instruments ADS8328

2,7 V ~ 5,5 V, 16 Bit 500KSPS Serieller ADC mit 2-zu-1-MUX

Datenblätter

Herunterladen
Low Power, 16-Bit, 500-kHz, Single/Dual Unipolar Input, ADC w/Serial I/F datasheet
PDF, 1.8 Mb, Revision: E, Datei veröffentlicht: Jan 27, 2011
Auszug aus dem Dokument

Preise

Status

ADS8328IBPWADS8328IBPWG4ADS8328IBRSATADS8328IPWADS8328IPWG4ADS8328IPWRADS8328IRSAT
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNo

Verpackung

ADS8328IBPWADS8328IBPWG4ADS8328IBRSATADS8328IPWADS8328IPWG4ADS8328IPWRADS8328IRSAT
N1234567
Pin16161616161616
Package TypePWPWRSAPWPWPWRSA
Industry STD TermTSSOPTSSOPVQFNTSSOPTSSOPTSSOPVQFN
JEDEC CodeR-PDSO-GR-PDSO-GS-PQFP-NR-PDSO-GR-PDSO-GR-PDSO-GS-PQFP-N
Package QTY909025090902000250
CarrierTUBETUBESMALL T&RTUBETUBELARGE T&RSMALL T&R
Device Marking8328I AADS8328I AADS8328I AADS8328I A
Width (mm)4.44.444.44.44.44
Length (mm)5545554
Thickness (mm)11.9111.9
Pitch (mm).65.65.65.65.65.65.65
Max Height (mm)1.21.211.21.21.21
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen

Parameter

Parameters / ModelsADS8328IBPW
ADS8328IBPW		ADS8328IBPWG4
ADS8328IBPWG4		ADS8328IBRSAT
ADS8328IBRSAT		ADS8328IPW
ADS8328IPW		ADS8328IPWG4
ADS8328IPWG4		ADS8328IPWR
ADS8328IPWR		ADS8328IRSAT
ADS8328IRSAT
# Input Channels2222222
Analog Voltage AVDD(Max), V5.55.55.55.55.55.55.5
Analog Voltage AVDD(Min), V2.72.72.72.72.72.72.7
ArchitectureSARSARSARSARSARSARSAR
Digital Supply(Max), V5.55.55.55.55.55.55.5
Digital Supply(Min), V1.651.651.651.651.651.651.65
INL(Max), +/-LSB2222222
Input Range(Max), V5.55.55.55.55.55.55.5
Input TypeDifferential,Single-EndedDifferential,Single-EndedDifferential,Single-EndedDifferential,Single-EndedDifferential,Single-EndedDifferential,Single-EndedDifferential,Single-Ended
Integrated FeaturesDaisy-Chainable,OscillatorDaisy-Chainable,OscillatorDaisy-Chainable,OscillatorDaisy-Chainable,OscillatorDaisy-Chainable,OscillatorDaisy-Chainable,OscillatorDaisy-Chainable,Oscillator
InterfaceSPISPISPISPISPISPISPI
Multi-Channel ConfigurationMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexed
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Package GroupTSSOPTSSOPQFNTSSOPTSSOPTSSOPQFN
Package Size: mm2:W x L, PKG16TSSOP: 32 mm2: 6.4 x 5(TSSOP)16TSSOP: 32 mm2: 6.4 x 5(TSSOP)16QFN: 16 mm2: 4 x 4(QFN)16TSSOP: 32 mm2: 6.4 x 5(TSSOP)16TSSOP: 32 mm2: 6.4 x 5(TSSOP)16TSSOP: 32 mm2: 6.4 x 5(TSSOP)16QFN: 16 mm2: 4 x 4(QFN)
Power Consumption(Typ), mW10.610.610.610.610.610.610.6
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Reference ModeExtExtExtExtExtExtExt
Resolution, Bits16161616161616
SINAD, dB91919191919191
SNR, dB91919191919191
Sample Rate (max), SPS500kSPS500kSPS500kSPS500kSPS500kSPS500kSPS500kSPS
Sample Rate(Max), MSPS0.50.50.50.50.50.50.5
THD(Typ), dB-98-98-98-98-98-98-98

Öko-Plan

ADS8328IBPWADS8328IBPWG4ADS8328IBRSATADS8328IPWADS8328IPWG4ADS8328IPWRADS8328IRSAT
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliant

Anwendungshinweise

  • Herunterladen
    Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, Revision: A, Datei veröffentlicht: Nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Herunterladen
    Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, Datei veröffentlicht: Mar 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
  • Herunterladen
    Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revision: A, Datei veröffentlicht: May 18, 2015
  • Herunterladen
    A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revision: B, Datei veröffentlicht: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Herunterladen
    Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revision: A, Datei veröffentlicht: Apr 16, 2015

Modellreihe

Serie: ADS8328 (7)

Herstellerklassifikation

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)