Datasheet Texas Instruments ADS805 — Datenblatt
Hersteller | Texas Instruments |
Serie | ADS805 |
12-Bit-Analog-Digital-Wandler (ADC) mit 20 MSPS
Datenblätter
12-Bit, 20MHz Sampling Analog-To-Digital Converter (Rev. B)
PDF, 862 Kb, Revision: B, Datei veröffentlicht: Jul 18, 2002
12-Bit, 20MHz Sampling Analog-To-Digital Converter datasheet
PDF, 812 Kb, Revision: B, Datei veröffentlicht: Jul 18, 2002
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Preise
Status
ADS805E | ADS805E/1K | ADS805EG4 | ADS805U | ADS805U/1K | |
---|---|---|---|---|---|
Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Obsolete (Manufacturer has discontinued the production of the device) | Obsolete (Manufacturer has discontinued the production of the device) |
Manufacture's Sample Availability | No | No | No | No | No |
Verpackung
ADS805E | ADS805E/1K | ADS805EG4 | ADS805U | ADS805U/1K | |
---|---|---|---|---|---|
N | 1 | 2 | 3 | 4 | 5 |
Pin | 28 | 28 | 28 | 28 | 28 |
Package Type | DB | DB | DB | DW | DW |
Industry STD Term | SSOP | SSOP | SSOP | SOIC | SOIC |
JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
Package QTY | 50 | 1000 | 50 | ||
Carrier | TUBE | LARGE T&R | TUBE | ||
Device Marking | ADS805E | ADS805E | ADS805E | ||
Width (mm) | 5.3 | 5.3 | 5.3 | 7.5 | 7.5 |
Length (mm) | 10.2 | 10.2 | 10.2 | 17.9 | 17.9 |
Thickness (mm) | 1.95 | 1.95 | 1.95 | 2.35 | 2.35 |
Pitch (mm) | .65 | .65 | .65 | 1.27 | 1.27 |
Max Height (mm) | 2 | 2 | 2 | 2.65 | 2.65 |
Mechanical Data | Herunterladen | Herunterladen | Herunterladen | Herunterladen | Herunterladen |
Parameter
Parameters / Models | ADS805E | ADS805E/1K | ADS805EG4 | ADS805U | ADS805U/1K |
---|---|---|---|---|---|
# Input Channels | 1 | 1 | 1 | 1 | 1 |
Analog Input BW, MHz | 270 | 270 | |||
Analog Input BW(MHz) | 270 | 270 | 270 | ||
Approx. Price (US$) | 11.95 | 1ku | 11.95 | 1ku | 11.95 | 1ku | ||
Architecture | Pipeline | Pipeline | Pipeline | Pipeline | Pipeline |
DNL(Max), +/-LSB | 0.75 | 0.75 | |||
DNL(Max)(+/-LSB) | 0.75 | 0.75 | 0.75 | ||
DNL(Typ), +/-LSB | 0.25 | 0.25 | |||
ENOB, Bits | 10.7 | 10.7 | |||
ENOB(Bits) | 0.25 | 0.25 | 0.25 | ||
INL(Max), +/-LSB | 2 | 2 | |||
INL(Max)(+/-LSB) | 1 | 1 | 1 | ||
INL(Typ), +/-LSB | 1 | 1 | |||
Input Buffer | No | No | No | No | |
Input Range | 2,5 | 2,5 | 2V / 5V(p-p) | 2V / 5V(p-p) | 2V / 5V(p-p) |
Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
Operating Temperature Range, C | -40 to 85 | -40 to 85 | |||
Operating Temperature Range(C) | -40 to 85 | -40 to 85 | -40 to 85 | ||
Package Group | SSOP | SSOP | SSOP | SSOP | SSOP |
Package Size(mm2=WxL) | 28SSOP: 80 mm2: 7.8 x 10.2 | ||||
Package Size: mm2:W x L, PKG | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) | |||
Package Size: mm2:W x L (PKG) | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) | |||
Power Consumption(Typ), mW | 300 | 300 | |||
Power Consumption(Typ)(mW) | 300 | 300 | 300 | ||
Rating | Catalog | Catalog | Catalog | Catalog | Catalog |
Reference Mode | Ext,Int | Ext,Int | Int Ext | Ext Int | Ext Int |
Resolution, Bits | 12 | 12 | |||
Resolution(Bits) | 12 | 12 | 12 | ||
SFDR, dB | 74 | 74 | |||
SFDR(dB) | 74 | 74 | 74 | ||
SINAD, dB | 66 | 66 | |||
SINAD(dB) | 66 | 66 | 66 | ||
SNR, dB | 68 | 68 | |||
SNR(dB) | 68 | 68 | 68 | ||
Sample Rate (max)(SPS) | 20MSPS | ||||
Sample Rate(Max), MSPS | 20 | 20 | |||
Sample Rate(Max)(MSPS) | 20 | 20 |
Öko-Plan
ADS805E | ADS805E/1K | ADS805EG4 | ADS805U | ADS805U/1K | |
---|---|---|---|---|---|
RoHS | Compliant | Compliant | Compliant | Not Compliant | Not Compliant |
Pb Free | Yes | No | No |
Anwendungshinweise
- CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Kb, Datei veröffentlicht: Sep 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, Datei veröffentlicht: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revision: A, Datei veröffentlicht: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, Datei veröffentlicht: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, Datei veröffentlicht: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, Revision: A, Datei veröffentlicht: Apr 16, 2015
- Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revision: A, Datei veröffentlicht: May 18, 2015
- Interleaving Analog-to-Digital ConvertersPDF, 64 Kb, Datei veröffentlicht: Oct 2, 2000
It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration several possible sources of error. - A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revision: B, Datei veröffentlicht: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - What Designers Should Know About Data Converter DriftPDF, 95 Kb, Datei veröffentlicht: Oct 2, 2000
Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its operating-temperature extremes, perhaps only to 9 or even 8 bits. But for lack of more precise knowledge, many play it safe (and expensive) and overspecify.
Modellreihe
Serie: ADS805 (5)
Herstellerklassifikation
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)