Datasheet Texas Instruments ADS5270 — Datenblatt
| Hersteller | Texas Instruments |
| Serie | ADS5270 |
Achtkanaliger 12-Bit-Analog-Digital-Wandler (ADC) mit 40 MSPS
Datenblätter
8-Channel, 12-Bit, 40MSPS Analog-to-Digital Converter with Serial LVDS Interface datasheet
PDF, 1.3 Mb, Revision: F, Datei veröffentlicht: Jan 6, 2009
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Preise
Status
| ADS5270IPFP | ADS5270IPFPT | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No |
Verpackung
| ADS5270IPFP | ADS5270IPFPT | |
|---|---|---|
| N | 1 | 2 |
| Pin | 80 | 80 |
| Package Type | PFP | PFP |
| Industry STD Term | HTQFP | HTQFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G |
| Package QTY | 96 | 250 |
| Carrier | JEDEC TRAY (10+1) | SMALL T&R |
| Device Marking | ADS5270IPFP | ADS5270IPFP |
| Width (mm) | 12 | 12 |
| Length (mm) | 12 | 12 |
| Thickness (mm) | 1 | 1 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | Herunterladen | Herunterladen |
Parameter
| Parameters / Models | ADS5270IPFP | ADS5270IPFPT |
|---|---|---|
| # Input Channels | 8 | 8 |
| Analog Input BW, MHz | 300 | 300 |
| Architecture | Pipeline | Pipeline |
| DNL(Max), +/-LSB | 0.5 | 0.5 |
| DNL(Typ), +/-LSB | 0.5 | 0.5 |
| ENOB, Bits | 11.3 | 11.3 |
| INL(Max), +/-LSB | 0.6 | 0.6 |
| INL(Typ), +/-LSB | 0.6 | 0.6 |
| Input Buffer | No | No |
| Input Range, Vp-p | 2 | 2 |
| Interface | Parallel LVDS | Parallel LVDS |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 |
| Package Group | HTQFP | HTQFP |
| Package Size: mm2:W x L, PKG | 80HTQFP: 196 mm2: 14 x 14(HTQFP) | 80HTQFP: 196 mm2: 14 x 14(HTQFP) |
| Power Consumption(Typ), mW | 907 | 907 |
| Rating | Catalog | Catalog |
| Reference Mode | Ext,Int | Ext,Int |
| Resolution, Bits | 12 | 12 |
| SFDR, dB | 85 | 85 |
| SINAD, dB | 70 | 70 |
| SNR, dB | 70.5 | 70.5 |
| Sample Rate(Max), MSPS | 40 | 40 |
Öko-Plan
| ADS5270IPFP | ADS5270IPFPT | |
|---|---|---|
| RoHS | Compliant | Compliant |
Anwendungshinweise
- Using the ADSDeSer-50EVM to Deserialize ADS527x 10-Bit OutputsPDF, 104 Kb, Datei veröffentlicht: Jul 8, 2004
The ADSDeSer-50EVM provides an direct means of examining the serialized 10-bit data output from the ADS527x families of serialized low voltage differential signal(LVDS) data converters by deserializing the data and converting to a parallel data port. This application report discusses the process of reading deserialized 10-bit data outputs from the ADS527x family using the ADSDeSer50-EVM. - LVDS Outputs on the ADS527xPDF, 236 Kb, Datei veröffentlicht: Jun 10, 2004
- Interfacing High-Speed LVDS Outputs of the ADS527x/ADS524xPDF, 67 Kb, Datei veröffentlicht: Feb 23, 2005
The ADS527x and ADS524x families of devices are high-performance octal/quad channel analog-to-digital converters, ideal for the highest system density. Serial low voltage differential signaling (LVDS) outputs reduce the number of I/O interfaces required, power and overall package size. These device families are rated to work from sampling rates of 20MSPS to 70MSPS, corresponding to data rates of 2 - Interfacing the VCA8613 with High-Speed ADCsPDF, 78 Kb, Datei veröffentlicht: Apr 5, 2005
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The VCA8617 is an 8-channel variable gain amplifier ideally suited for portable and mid-range ultrasound applications. Each channel consists of a Low Noise Amplifier (LNA) and a Variable Gain Amplifier (VGA). The VGA contains two parts: a voltage-controlled attenuator and a programmable gain amplifier. The PGA output feeds directly into an integrated 3-pole low-pass Butterworth filter, which preve - CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Kb, Datei veröffentlicht: Sep 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Mb, Revision: A, Datei veröffentlicht: Jul 19, 2013
- Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Mb, Revision: A, Datei veröffentlicht: May 22, 2015
- Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, Datei veröffentlicht: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revision: A, Datei veröffentlicht: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, Datei veröffentlicht: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, Datei veröffentlicht: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, Revision: A, Datei veröffentlicht: Apr 16, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revision: B, Datei veröffentlicht: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revision: A, Datei veröffentlicht: May 18, 2015
Modellreihe
Serie: ADS5270 (2)
Herstellerklassifikation
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)