Datasheet Texas Instruments 66AK2L06 — Datenblatt
| Hersteller | Texas Instruments |
| Serie | 66AK2L06 |
Multicore DSP + ARM KeyStone II System-on-Chip (SoC)
Datenblätter
66AK2L06 Multicore DSP+ARM KeyStone II System-on-Chip (SoC) datasheet
PDF, 1.9 Mb, Datei veröffentlicht: Apr 21, 2015
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Preise
Status
| 66AK2L06XCMS | 66AK2L06XCMS2 | 66AK2L06XCMSA | 66AK2L06XCMSA2 | |
|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | Yes | Yes | Yes |
Verpackung
| 66AK2L06XCMS | 66AK2L06XCMS2 | 66AK2L06XCMSA | 66AK2L06XCMSA2 | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 900 | 900 | 900 | 900 |
| Package Type | CMS | CMS | CMS | CMS |
| Package QTY | 44 | 44 | 44 | 44 |
| Device Marking | 66AK2L06XCMS | 66AK2L06XCMS | A1GHZ | @2013 |
| Width (mm) | 25 | 25 | 25 | 25 |
| Length (mm) | 25 | 25 | 25 | 25 |
| Thickness (mm) | 2.98 | 2.98 | 2.98 | 2.98 |
| Mechanical Data | Herunterladen | Herunterladen | Herunterladen | Herunterladen |
Parameter
| Parameters / Models | 66AK2L06XCMS | 66AK2L06XCMS2 | 66AK2L06XCMSA | 66AK2L06XCMSA2 |
|---|---|---|---|---|
| ARM CPU | 2 ARM Cortex-A15 | 2 ARM Cortex-A15 | 2 ARM Cortex-A15 | 2 ARM Cortex-A15 |
| ARM MHz, Max. | 1200 | 1200 | 1200 | 1200 |
| Applications | Avionics and Defense,Medical,Test and Measurement | Avionics and Defense,Medical,Test and Measurement | Avionics and Defense,Medical,Test and Measurement | Avionics and Defense,Medical,Test and Measurement |
| DRAM | DDR3,DDR3L | DDR3,DDR3L | DDR3,DDR3L | DDR3,DDR3L |
| DSP | 4 C66x | 4 C66x | 4 C66x | 4 C66x |
| DSP MHz, Max. | 1200 | 1200 | 1200 | 1200 |
| EMAC | 4-port 1Gb Switch | 4-port 1Gb Switch | 4-port 1Gb Switch | 4-port 1Gb Switch |
| Hardware Accelerators | FFT Coprocessor,Digital Front End | FFT Coprocessor,Digital Front End | FFT Coprocessor,Digital Front End | FFT Coprocessor,Digital Front End |
| I2C | 3 | 3 | 3 | 3 |
| JESD204B | 4 Lanes | 4 Lanes | 4 Lanes | 4 Lanes |
| On-Chip L2 Cache | 1024 KB (ARM Cluster),1024 KB (per C66x DSP core) | 1024 KB (ARM Cluster),1024 KB (per C66x DSP core) | 1024 KB (ARM Cluster),1024 KB (per C66x DSP core) | 1024 KB (ARM Cluster),1024 KB (per C66x DSP core) |
| Operating Systems | Integrity,Linux,SYS/BIOS,VxWorks | Integrity,Linux,SYS/BIOS,VxWorks | Integrity,Linux,SYS/BIOS,VxWorks | Integrity,Linux,SYS/BIOS,VxWorks |
| Operating Temperature Range, C | -40 to 100,0 to 100 | -40 to 100,0 to 100 | -40 to 100,0 to 100 | -40 to 100,0 to 100 |
| Other On-Chip Memory | 3072 KB | 3072 KB | 3072 KB | 3072 KB |
| PCI/PCIe | 2 PCIe Gen2 | 2 PCIe Gen2 | 2 PCIe Gen2 | 2 PCIe Gen2 |
| Rating | Catalog | Catalog | Catalog | Catalog |
| SPI | 3 | 3 | 3 | 3 |
| UART, SCI | 4 | 4 | 4 | 4 |
| USB | 1 | 1 | 1 | 1 |
Öko-Plan
| 66AK2L06XCMS | 66AK2L06XCMS2 | 66AK2L06XCMSA | 66AK2L06XCMSA2 | |
|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant |
Anwendungshinweise
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This application report describes an application circuit example of the TPS544B/Cxx family of power management IC (PMIC) powering the Smart-Reflex digital core supply of the TCI6630K2L SoC. Smart-Reflex Class 0 Temperature Compensation (Class 0 TC) mode of operation of the TCI6630K2L device is emphasized. Assumption is that temperature compensation mode is enabled using the function provided in th - 66AK2L06 JESD Attach to ADC12J4000/DAC38J84 Getting Started Guide (Rev. B)PDF, 8.8 Mb, Revision: B, Datei veröffentlicht: Jun 20, 2016
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- Keystone II DDR3 InitializationPDF, 73 Kb, Datei veröffentlicht: Jan 26, 2015
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This application report lists the steps to enable Class 0 Temperature Compensation (Class 0 TC) mode of SmartReflexв„ў Subsystem (SRSS) module available on such devices. - Throughput Performance Guide for KeyStone II Devices (Rev. B)PDF, 866 Kb, Revision: B, Datei veröffentlicht: Dec 22, 2015
This application report analyzes various performance measurements of the KeyStone II family of processors. It provides a throughput analysis of the various support peripherals to different end-points and memory access. - Keystone II DDR3 Debug GuidePDF, 143 Kb, Datei veröffentlicht: Oct 16, 2015
This guide provides tools for use when debugging a failing DDR3 interface on a KeyStone II device. - Hardware Design Guide for KeyStone II DevicesPDF, 1.8 Mb, Datei veröffentlicht: Mar 24, 2014
- SERDES Link Commissioning on KeyStone I and II DevicesPDF, 138 Kb, Datei veröffentlicht: Apr 13, 2016
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- Optimizing Loops on the C66x DSPPDF, 585 Kb, Datei veröffentlicht: Nov 9, 2010
- The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)PDF, 20 Kb, Revision: A, Datei veröffentlicht: Nov 10, 2010
The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM - Clocking Design Guide for KeyStone DevicesPDF, 1.5 Mb, Datei veröffentlicht: Nov 9, 2010
- DDR3 Design Requirements for KeyStone Devices (Rev. B)PDF, 582 Kb, Revision: B, Datei veröffentlicht: Jun 5, 2014
- Multicore Programming Guide (Rev. B)PDF, 1.8 Mb, Revision: B, Datei veröffentlicht: Aug 29, 2012
As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore - TI DSP BenchmarkingPDF, 62 Kb, Datei veröffentlicht: Jan 13, 2016
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This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal require
Modellreihe
Serie: 66AK2L06 (4)
Herstellerklassifikation
- Semiconductors> Processors> Digital Signal Processors> C6000 DSP + ARM Processors> 66AK2x