Datasheet Texas Instruments 66AK2H14 — Datenblatt

HerstellerTexas Instruments
Serie66AK2H14
Datasheet Texas Instruments 66AK2H14

Multicore DSP + ARM KeyStone II System-on-Chip (SoC)

Datenblätter

66AK2Hxx Multicore DSP+ARMВ® KeyStone II System-on-Chip (SoC) datasheet
PDF, 2.4 Mb, Revision: F, Datei veröffentlicht: Jun 2, 2017
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Preise

Status

66AK2H14BAAW2466AK2H14BAAWA2466AK2H14BXAAW2466AK2H14DAAW2466AK2H14DAAWA2466AK2H14DXAAWA24
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoYesNoNoNo

Verpackung

66AK2H14BAAW2466AK2H14BAAWA2466AK2H14BXAAW2466AK2H14DAAW2466AK2H14DAAWA2466AK2H14DXAAWA24
N123456
Pin151715171517151715171517
Package TypeAAWAAWAAWAAWAAWAAW
Package QTY21212121211
CarrierJEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)
Device Marking66AK2H14AAWA1.2GHZ/1.4GHZ1.2GHZ/1.4GHZ1.2GHZ/1.4GHZA1.2GHZ/1.4GHZ@2012 TI
Width (mm)404040404040
Length (mm)404040404040
Thickness (mm)3.073.073.073.073.073.07
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen

Parameter

Parameters / Models66AK2H14BAAW24
66AK2H14BAAW24
66AK2H14BAAWA24
66AK2H14BAAWA24
66AK2H14BXAAW24
66AK2H14BXAAW24
66AK2H14DAAW24
66AK2H14DAAW24
66AK2H14DAAWA24
66AK2H14DAAWA24
66AK2H14DXAAWA24
66AK2H14DXAAWA24
ARM CPU4 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A15
ARM MHz, Max.1200,14001200,14001200,14001200,14001200,14001200,1400
ApplicationsAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,Space
DRAMDDR3,DDR3LDDR3,DDR3LDDR3,DDR3LDDR3,DDR3LDDR3,DDR3LDDR3,DDR3L
DSP8 C66x8 C66x8 C66x8 C66x8 C66x8 C66x
DSP MHz, Max.120012001200120012001200
EMAC10G Ethernet10G Ethernet10G Ethernet10G Ethernet10G Ethernet10G Ethernet
Hardware AcceleratorsPacket Accelerator,Security AcceleratorPacket Accelerator,Security AcceleratorPacket Accelerator,Security AcceleratorPacket Accelerator,Security AcceleratorPacket Accelerator,Security AcceleratorPacket Accelerator,Security Accelerator
I2C333333
On-Chip L2 Cache4096 KB (ARM Cluster),1024 KB (per C66x DSP core)4096 KB (ARM Cluster),1024 KB (per C66x DSP core)4096 KB (ARM Cluster),1024 KB (per C66x DSP core)4096 KB (ARM Cluster),1024 KB (per C66x DSP core)4096 KB (ARM Cluster),1024 KB (per C66x DSP core)4096 KB (ARM Cluster),1024 KB (per C66x DSP core)
Operating SystemsIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorks
Operating Temperature Range, C-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85
Other On-Chip Memory6144 KB6144 KB6144 KB6144 KB6144 KB6144 KB
PCI/PCIe2 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen2
RatingCatalogCatalogCatalogCatalogCatalogCatalog
SPI333333
UART, SCI222222
USB111111

Öko-Plan

66AK2H14BAAW2466AK2H14BAAWA2466AK2H14BXAAW2466AK2H14DAAW2466AK2H14DAAWA2466AK2H14DXAAWA24
RoHSCompliantCompliantCompliantCompliantCompliantCompliant

Anwendungshinweise

  • PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A)
    PDF, 57 Kb, Revision: A, Datei veröffentlicht: May 19, 2017
  • Keystone II DDR3 Initialization
    PDF, 73 Kb, Datei veröffentlicht: Jan 26, 2015
    This application report provides a step-to-step initialization guide for the Keystone II device DDR3 SDRAM controller.
  • Throughput Performance Guide for KeyStone II Devices (Rev. B)
    PDF, 866 Kb, Revision: B, Datei veröffentlicht: Dec 22, 2015
    This application report analyzes various performance measurements of the KeyStone II family of processors. It provides a throughput analysis of the various support peripherals to different end-points and memory access.
  • Keystone II DDR3 Debug Guide
    PDF, 143 Kb, Datei veröffentlicht: Oct 16, 2015
    This guide provides tools for use when debugging a failing DDR3 interface on a KeyStone II device.
  • Power Management of KS2 Device (Rev. C)
    PDF, 61 Kb, Revision: C, Datei veröffentlicht: Jul 15, 2016
    This application report lists the steps to enable Class 0 Temperature Compensation (Class 0 TC) mode of SmartReflexв„ў Subsystem (SRSS) module available on such devices.
  • Hardware Design Guide for KeyStone II Devices
    PDF, 1.8 Mb, Datei veröffentlicht: Mar 24, 2014
  • SERDES Link Commissioning on KeyStone I and II Devices
    PDF, 138 Kb, Datei veröffentlicht: Apr 13, 2016
    The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.
  • PCIe Use Cases for KeyStone Devices
    PDF, 320 Kb, Datei veröffentlicht: Dec 13, 2011
  • The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)
    PDF, 20 Kb, Revision: A, Datei veröffentlicht: Nov 10, 2010
    The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
  • Clocking Design Guide for KeyStone Devices
    PDF, 1.5 Mb, Datei veröffentlicht: Nov 9, 2010
  • Optimizing Loops on the C66x DSP
    PDF, 585 Kb, Datei veröffentlicht: Nov 9, 2010
  • DDR3 Design Requirements for KeyStone Devices (Rev. B)
    PDF, 582 Kb, Revision: B, Datei veröffentlicht: Jun 5, 2014
  • Multicore Programming Guide (Rev. B)
    PDF, 1.8 Mb, Revision: B, Datei veröffentlicht: Aug 29, 2012
    As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
  • TI DSP Benchmarking
    PDF, 62 Kb, Datei veröffentlicht: Jan 13, 2016
    This application report provides benchmarks for the C674x DSP core, the C66x DSP core and the ARMВ®CortexВ®-A15 core. This document also shows how to reproduce these benchmarks on specific hardware platforms.
  • Thermal Design Guide for DSP and ARM Application Processors (Rev. A)
    PDF, 324 Kb, Revision: A, Datei veröffentlicht: Aug 17, 2016
    This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal require

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Herstellerklassifikation

  • Semiconductors> Processors> Digital Signal Processors> C6000 DSP + ARM Processors> 66AK2x