Datasheet Texas Instruments 66AK2E05 — Datenblatt

HerstellerTexas Instruments
Serie66AK2E05
Datasheet Texas Instruments 66AK2E05

Multicore DSP + ARM KeyStone II System-on-Chip (SoC)

Datenblätter

66AK2E05/02 Multicore DSP+ARM KeyStone II System-on-Chip (SoC) datasheet
PDF, 2.0 Mb, Revision: D, Datei veröffentlicht: Mar 11, 2015
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Preise

Status

66AK2E05XABD2566AK2E05XABD466AK2E05XABDA2566AK2E05XABDA4X66AK2E05XABD25
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoYesNoNoNo

Verpackung

66AK2E05XABD2566AK2E05XABD466AK2E05XABDA2566AK2E05XABDA4X66AK2E05XABD25
N12345
Pin10891089108910891089
Package TypeABDABDABDABDABD
Package QTY4040401
CarrierJEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)
Device Marking@2012 TI@2012 TIA1.25GHZ66AK2E05XABD@2012 TI
Width (mm)2727272727
Length (mm)2727272727
Thickness (mm)2.982.982.982.982.98
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen

Parameter

Parameters / Models66AK2E05XABD25
66AK2E05XABD25
66AK2E05XABD4
66AK2E05XABD4
66AK2E05XABDA25
66AK2E05XABDA25
66AK2E05XABDA4
66AK2E05XABDA4
X66AK2E05XABD25
X66AK2E05XABD25
ARM CPU4 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A15
ARM MHz, Max.1250,14001250,14001250,14001250,14001250,1400
ApplicationsAvionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAvionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAvionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAvionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAvionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,Space
DRAMDDR3,DDR3LDDR3,DDR3LDDR3,DDR3LDDR3,DDR3LDDR3,DDR3L
DSP1 C66x1 C66x1 C66x1 C66x1 C66x
DSP MHz, Max.1250,14001250,14001250,14001250,14001250,1400
EMAC2-Port 10Gb Switch,8-Port 1Gb Switch2-Port 10Gb Switch,8-Port 1Gb Switch2-Port 10Gb Switch,8-Port 1Gb Switch2-Port 10Gb Switch,8-Port 1Gb Switch2-Port 10Gb Switch,8-Port 1Gb Switch
Hardware AcceleratorsSecurity Accelerator,Packet AcceleratorSecurity Accelerator,Packet AcceleratorSecurity Accelerator,Packet AcceleratorSecurity Accelerator,Packet AcceleratorSecurity Accelerator,Packet Accelerator
I2C33333
On-Chip L2 Cache4096 KB (ARM Cluster),512 KB (per C66x DSP core)4096 KB (ARM Cluster),512 KB (per C66x DSP core)4096 KB (ARM Cluster),512 KB (per C66x DSP core)4096 KB (ARM Cluster),512 KB (per C66x DSP core)4096 KB (ARM Cluster),512 KB (per C66x DSP core)
Operating SystemsIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorks
Operating Temperature Range, C0 to 85,-40 to 1000 to 85,-40 to 1000 to 85,-40 to 1000 to 85,-40 to 1000 to 85,-40 to 100
Other On-Chip Memory2048 KB2048 KB2048 KB2048 KB2048 KB
PCI/PCIe4 PCIe Gen24 PCIe Gen24 PCIe Gen24 PCIe Gen24 PCIe Gen2
RatingCatalogCatalogCatalogCatalogCatalog
SPI33333
UART, SCI22222
USB22222

Öko-Plan

66AK2E05XABD2566AK2E05XABD466AK2E05XABDA2566AK2E05XABDA4X66AK2E05XABD25
RoHSCompliantCompliantCompliantCompliantNot Compliant

Anwendungshinweise

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    This application report discusses estimating the power consumption of Texas Instruments' K2Ex Digital Signal Processors (DSP) using a provided device-specific power spreadsheet. It should be noted that the power model is applicable for all silicon revisions.
  • Clocking Spreadsheet for K2E Device Family
    PDF, 22 Kb, Datei veröffentlicht: Jan 26, 2017
    This document discusses the internal clocking architecture of Texas Instruments K2Ex Digital Signal Processors (DSP) using a provided clocking spreadsheet.The 66AK2Ex and AM5K2Ex devices have similar internal clocking architecture and peripherals except the corepac. The 66AK2Ex devices have both DSP corepac and ARM corepac, whereas, the AM5K2Ex devices have ARM corepac only.Use the K
  • PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A)
    PDF, 57 Kb, Revision: A, Datei veröffentlicht: May 19, 2017
  • Keystone II DDR3 Initialization
    PDF, 73 Kb, Datei veröffentlicht: Jan 26, 2015
    This application report provides a step-to-step initialization guide for the Keystone II device DDR3 SDRAM controller.
  • Throughput Performance Guide for KeyStone II Devices (Rev. B)
    PDF, 866 Kb, Revision: B, Datei veröffentlicht: Dec 22, 2015
    This application report analyzes various performance measurements of the KeyStone II family of processors. It provides a throughput analysis of the various support peripherals to different end-points and memory access.
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    PDF, 143 Kb, Datei veröffentlicht: Oct 16, 2015
    This guide provides tools for use when debugging a failing DDR3 interface on a KeyStone II device.
  • Power Management of KS2 Device (Rev. C)
    PDF, 61 Kb, Revision: C, Datei veröffentlicht: Jul 15, 2016
    This application report lists the steps to enable Class 0 Temperature Compensation (Class 0 TC) mode of SmartReflexв„ў Subsystem (SRSS) module available on such devices.
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    PDF, 138 Kb, Datei veröffentlicht: Apr 13, 2016
    The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.
  • PCIe Use Cases for KeyStone Devices
    PDF, 320 Kb, Datei veröffentlicht: Dec 13, 2011
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    PDF, 1.5 Mb, Datei veröffentlicht: Nov 9, 2010
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    PDF, 20 Kb, Revision: A, Datei veröffentlicht: Nov 10, 2010
    The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
  • Optimizing Loops on the C66x DSP
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  • DDR3 Design Requirements for KeyStone Devices (Rev. B)
    PDF, 582 Kb, Revision: B, Datei veröffentlicht: Jun 5, 2014
  • Multicore Programming Guide (Rev. B)
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  • Processor SDK RTOS Audio Benchmark Starter Kit
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    The TI TMS320C6000в„ў Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications that are commonly used in audio processing application. This application notes describes Audio Benchmark Starterkit software that is intended to provide an easy and quick way to benchmark key audio functions on C66x and C674x DSP device
  • TI DSP Benchmarking
    PDF, 62 Kb, Datei veröffentlicht: Jan 13, 2016
    This application report provides benchmarks for the C674x DSP core, the C66x DSP core and the ARMВ®CortexВ®-A15 core. This document also shows how to reproduce these benchmarks on specific hardware platforms.

Modellreihe

Herstellerklassifikation

  • Semiconductors> Processors> Digital Signal Processors> C6000 DSP + ARM Processors> 66AK2x