Datasheet Texas Instruments CD74HC112PWT — Datenblatt
| Hersteller | Texas Instruments |
| Serie | CD74HC112 |
| Artikelnummer | CD74HC112PWT |
Hochgeschwindigkeits-CMOS-Logik-Dual-Negative-Edge-Triggered JK-Flip-Flops mit Set und Reset 16-TSSOP -55 bis 125
Datenblätter
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 datasheet
PDF, 749 Kb, Revision: H, Datei veröffentlicht: Oct 13, 2003
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Preise
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Verpackung
| Pin | 16 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 250 |
| Carrier | SMALL T&R |
| Device Marking | HJ112 |
| Width (mm) | 4.4 |
| Length (mm) | 5 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Herunterladen |
Parameter
| Bits | 2 |
| F @ Nom Voltage(Max) | 70 Mhz |
| ICC @ Nom Voltage(Max) | 0.04 mA |
| Output Drive (IOL/IOH)(Max) | -6/6 mA |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | HC |
| VCC(Max) | 6 V |
| VCC(Min) | 2 V |
| Voltage(Nom) | 3.3,5 V |
| tpd @ Nom Voltage(Max) | 53 ns |
Öko-Plan
| RoHS | Compliant |
Anwendungshinweise
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Modellreihe
Serie: CD74HC112 (9)
Herstellerklassifikation
- Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop