Datasheet Texas Instruments 74AVCH4T245PWRG4 — Datenblatt
| Hersteller | Texas Instruments |
| Serie | SN74AVCH4T245 |
| Artikelnummer | 74AVCH4T245PWRG4 |
4-Bit-Dual-Supply-Bus-Transceiver mit konfigurierbarer Spannungsumsetzung und 3-Zustands-Ausgängen 16-TSSOP -40 bis 85
Datenblätter
SN74AVCH4T245 4-Bit Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs datasheet
PDF, 1.5 Mb, Revision: E, Datei veröffentlicht: Nov 25, 2015
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Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Verpackung
| Pin | 16 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | WS245 |
| Width (mm) | 4.4 |
| Length (mm) | 5 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Herunterladen |
Parameter
| Bits | 4 |
| F @ Nom Voltage(Max) | 100 Mhz |
| ICC @ Nom Voltage(Max) | 0.016 mA |
| Operating Temperature Range | -40 to 85 C |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | AVC |
| VCC(Max) | 3.6 V |
| VCC(Min) | 1.2 V |
| Voltage(Nom) | 1.2,1.5,1.8,2.5,3.3 V |
| tpd @ Nom Voltage(Max) | 3.4,3.2,2.9,2.8 ns |
Öko-Plan
| RoHS | Compliant |
Design Kits und Evaluierungsmodule
- Evaluation Modules & Boards: LDC2114EVM
LDC2114 1.8V 4-Channel Inductive Touch Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: AVCLVCDIRCNTRL-EVM
Generic EVM for Direction-Controlled Bidirectional Translation Device Supporting AVC and LVC
Lifecycle Status: Active (Recommended for new designs)
Anwendungshinweise
- Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B)PDF, 126 Kb, Revision: B, Datei veröffentlicht: Jul 7, 1999
Texas Instruments (TI[TM]) next-generation logic is called the Advanced Very-low-voltage CMOS (AVC) family. The AVCfamily features TI?s Dynamic Output Control (DOC[TM]) circuit (patent pending). DOC circuitry automatically lowers the outputimpedance of the circuit at the beginning of a signal transition, providing enough current to achieve high signaling speeds, thensubsequently raises the i - AVC Logic Family Technology and Applications (Rev. A)PDF, 148 Kb, Revision: A, Datei veröffentlicht: Aug 26, 1998
Texas Instruments (TI?) announces the industry?s first logic family to achieve maximum propagation delays of less than 2 ns at 2.5 V. TI?s next-generation logic is the Advanced Very-low-voltage CMOS (AVC) family. Although optimized for 2.5-V systems, AVC logic supports mixed-voltage systems because it is compatible with 3.3-V and 1.8-V devices. The AVC family features TI?s Dynamic Output Control ( - Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)PDF, 390 Kb, Revision: B, Datei veröffentlicht: Apr 30, 2015
- 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)PDF, 895 Kb, Revision: B, Datei veröffentlicht: May 22, 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa - Selecting the Right Level Translation Solution (Rev. A)PDF, 313 Kb, Revision: A, Datei veröffentlicht: Jun 22, 2004
Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
Modellreihe
Serie: SN74AVCH4T245 (15)
Herstellerklassifikation
- Semiconductors > Logic > Voltage Level Translation > Direction Controlled Voltage Translation