Datasheet Texas Instruments CD74HC73E — Datenblatt
| Hersteller | Texas Instruments |
| Serie | CD74HC73 |
| Artikelnummer | CD74HC73E |
Hochgeschwindigkeits-CMOS-Logik-Dual-Negative-Edge-Triggered JK-Flip-Flops mit Reset 14-PDIP -55 auf 125
Datenblätter
CD54HC73, CD74HC73, CD74HCT73 datasheet
PDF, 724 Kb, Revision: E, Datei veröffentlicht: Aug 21, 2003
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Preise
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Verpackung
| Pin | 14 |
| Package Type | N |
| Industry STD Term | PDIP |
| JEDEC Code | R-PDIP-T |
| Package QTY | 25 |
| Carrier | TUBE |
| Device Marking | CD74HC73E |
| Width (mm) | 6.35 |
| Length (mm) | 19.3 |
| Thickness (mm) | 3.9 |
| Pitch (mm) | 2.54 |
| Max Height (mm) | 5.08 |
| Mechanical Data | Herunterladen |
Parameter
| Bits | 2 |
| F @ Nom Voltage(Max) | 70 Mhz |
| ICC @ Nom Voltage(Max) | 0.04 mA |
| Output Drive (IOL/IOH)(Max) | -6/6 mA |
| Package Group | PDIP |
| Package Size: mm2:W x L | See datasheet (PDIP) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | HC |
| VCC(Max) | 6 V |
| VCC(Min) | 2 V |
| Voltage(Nom) | 3.3,5 V |
| tpd @ Nom Voltage(Max) | 40 ns |
Öko-Plan
| RoHS | Compliant |
| Pb Free | Yes |
Anwendungshinweise
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015
- SN54/74HCT CMOS Logic Family Applications and RestrictionsPDF, 102 Kb, Datei veröffentlicht: May 1, 1996
The TI SN54/74HCT family of CMOS devices is a subgroup of the SN74HC series with the HCT circuitry modified to meet the interfacing requirements of TTL outputs to high-speed CMOS inputs. The HCT devices can be driven by the TTL circuits directly without additional components. This document describes the TTL/HC interface the operating voltages circuit noise and power consumption. A Bergeron anal
Modellreihe
Serie: CD74HC73 (7)
Herstellerklassifikation
- Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop