Datasheet Texas Instruments SN74LVTH574PWLE — Datenblatt

HerstellerTexas Instruments
SerieSN74LVTH574
ArtikelnummerSN74LVTH574PWLE
Datasheet Texas Instruments SN74LVTH574PWLE

3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops mit 3-State-Ausgängen 20-TSSOP -40 bis 85

Datenblätter

SN54LVTH574, SN74LVTH574 datasheet
PDF, 1.4 Mb, Revision: G, Datei veröffentlicht: Sep 15, 2003
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Preise

Status

Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)
Manufacture's Sample AvailabilityNo

Verpackung

Pin20
Package TypePW
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Width (mm)4.4
Length (mm)6.5
Thickness (mm)1
Pitch (mm).65
Max Height (mm)1.2
Mechanical DataHerunterladen

Ersatz

ReplacementSN74LVTH574PWR
Replacement CodeS

Parameter

3-State OutputYes
Approx. Price (US$)0.26 | 1ku
Bits(#)8
F @ Nom Voltage(Max)(Mhz)160
ICC @ Nom Voltage(Max)(mA)5
Input TypeTTL
Operating Temperature Range(C)-40 to 85
Output Drive (IOL/IOH)(Max)(mA)64/-32
Output TypeTTL
Package GroupTSSOP
Package Size: mm2:W x L (PKG)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
RatingCatalog
Schmitt TriggerNo
Technology FamilyLVT
VCC(Max)(V)3.6
VCC(Min)(V)2.7
Voltage(Nom)(V)3.3
tpd @ Nom Voltage(Max)(ns)4.5

Öko-Plan

RoHSNot Compliant
Pb FreeNo

Anwendungshinweise

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Modellreihe

Herstellerklassifikation

  • Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Flip-Flop