Datasheet Texas Instruments SN74LS280N3 — Datenblatt

Hersteller	Texas Instruments
Serie	SN74LS280
Artikelnummer	SN74LS280N3

9-Bit-Generatoren / Prüfer für ungerade / gerade Parität 14-PDIP 0 bis 70

Datenblätter

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PDF, 1.0 Mb, Datei veröffentlicht: Mar 1, 1988

Auszug aus dem Dokument

SN54LS280, SN54S280, SN74LS280, SN74S280
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
SDLS152 вЂ“ DECEMBER 1972 вЂ“ REVISED MARCH 1988 Copyright пЈ© 1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters. POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1 SN54LS280, SN54S280, SN74LS280, SN74S280
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
SDLS152 вЂ“ DECEMBER 1972 вЂ“ REVISED MARCH 1988 2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 SN54LS280, SN54S280, SN74LS280, SN74S280
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
SDLS152 вЂ“ DECEMBER 1972 вЂ“ REVISED MARCH 1988 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3 SN54LS280, SN54S280, SN74LS280, SN74S280
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
SDLS152 вЂ“ DECEMBER 1972 вЂ“ REVISED MARCH 1988 4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 SN54LS280, SN54S280, SN74LS280, SN74S280
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
SDLS152 вЂ“ DECEMBER 1972 вЂ“ REVISED MARCH 1988 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2017 PACKAGING INFORMATION
Orderable Device Status
(1) Package Type Package Pins Package
Drawing
Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (В°C) Device Marking
(4/5) JM38510/32901BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
32901BCA M38510/32901BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
32901BCA M38510/32901BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
32901BCA SN54LS280J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS280J SN54LS280J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS280J SN54S280J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54S280J SN54S280J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54S280J SN74LS280D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS280 SN74LS280D ACTIVE SOIC D 14 50 Green (RoHS …

Preise

Status

Lifecycle Status	Obsolete (Manufacturer has discontinued the production of the device)
Manufacture's Sample Availability	No

Verpackung

Pin	14
Package Type	N
Industry STD Term	PDIP
JEDEC Code	R-PDIP-T
Width (mm)	6.35
Length (mm)	19.3
Thickness (mm)	3.9
Pitch (mm)	2.54
Max Height (mm)	5.08
Mechanical Data	Herunterladen

Parameter

Approx. Price (US$)	0.45 \| 1ku
Bits(#)	2
F @ Nom Voltage(Max)(Mhz)	35
Function	Parity
ICC @ Nom Voltage(Max)(mA)	27
Input Type	TTL
Operating Temperature Range(C)	0 to 70
Output Drive (IOL/IOH)(Max)(mA)	8/-0.4
Output Type	CMOS
Package Group	PDIP
Package Size: mm2:W x L (PKG)	See datasheet (PDIP)
Rating	Catalog
Schmitt Trigger	No
Technology Family	LS
Type	Other
VCC(Max)(V)	5.25
VCC(Min)(V)	4.75
Voltage(Nom)(V)	5
tpd @ Nom Voltage(Max)(ns)	50

Öko-Plan

RoHS	Not Compliant
Pb Free	No

Anwendungshinweise

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Designing with the SN54/74LS123 (Rev. A)
PDF, 118 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1997
The Texas Instruments (TI) SN54/74LS123 dual retriggerable monostable multivibrator is a one-shot device capable of verylong output pulses and up to 100% duty cycle. The ?LS123 also features dc triggering from gated low-level active A andhigh-level active B inputs and provides a clear input that terminates the output pulse of any predetermined time independentof timing components R ext and

Modellreihe

Serie: SN74LS280 (5)

SN74LS280D SN74LS280J SN74LS280N SN74LS280N3 SN74LS280NSR

Herstellerklassifikation

Semiconductors > Logic > Specialty Logic > Counter/Arithmetic/Parity Function