Datasheet Texas Instruments CD74ACT74QM96G4Q1 — Datenblatt
Hersteller | Texas Instruments |
Serie | CD74ACT74-Q1 |
Artikelnummer | CD74ACT74QM96G4Q1 |
Automotive Catalogue Dual-Positive-Edge-Triggered D-Type Flip-Flops mit Set und Reset 14-SOIC -40 bis 125
Datenblätter
Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset datasheet
PDF, 203 Kb, Revision: A, Datei veröffentlicht: Jan 29, 2008
Auszug aus dem Dokument
Preise
Status
Lifecycle Status | Active (Recommended for new designs) |
Manufacture's Sample Availability | No |
Verpackung
Pin | 14 |
Package Type | D |
Industry STD Term | SOIC |
JEDEC Code | R-PDSO-G |
Package QTY | 2500 |
Carrier | LARGE T&R |
Device Marking | ACT74Q |
Width (mm) | 3.91 |
Length (mm) | 8.65 |
Thickness (mm) | 1.58 |
Pitch (mm) | 1.27 |
Max Height (mm) | 1.75 |
Mechanical Data | Herunterladen |
Parameter
3-State Output | No |
Bits | 2 |
F @ Nom Voltage(Max) | 90 Mhz |
ICC @ Nom Voltage(Max) | 0.04 mA |
Operating Temperature Range | -40 to 125 C |
Output Drive (IOL/IOH)(Max) | 24/-24 mA |
Package Group | SOIC |
Package Size: mm2:W x L | 14SOIC: 52 mm2: 6 x 8.65(SOIC) PKG |
Rating | Automotive |
Schmitt Trigger | No |
Technology Family | ACT |
VCC(Max) | 5.5 V |
VCC(Min) | 4.5 V |
Voltage(Nom) | 5 V |
tpd @ Nom Voltage(Max) | 8.6 ns |
Öko-Plan
RoHS | Compliant |
Anwendungshinweise
- Selecting the Right Level Translation Solution (Rev. A)PDF, 313 Kb, Revision: A, Datei veröffentlicht: Jun 22, 2004
Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati - Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, Datei veröffentlicht: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
Modellreihe
Serie: CD74ACT74-Q1 (2)
- CD74ACT74QM96G4Q1 CD74ACT74QM96Q1
Herstellerklassifikation
- Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Flip-Flop