Datasheet Texas Instruments DAC5674IPHP — Datenblatt

Hersteller	Texas Instruments
Serie	DAC5674
Artikelnummer	DAC5674IPHP

14-Bit, 400-MSPS, 2x-4x interpolierender Digital-Analog-Wandler (DAC) 48-HTQFP -40 bis 85

Datenblätter

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PDF, 1.3 Mb, Revision: A, Datei veröffentlicht: Oct 4, 2005

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Preise

Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Verpackung

Pin	48
Package Type	PHP
Industry STD Term	HTQFP
JEDEC Code	S-PQFP-G
Package QTY	250
Carrier	JEDEC TRAY (10+1)
Device Marking	DAC5674
Width (mm)	7
Length (mm)	7
Thickness (mm)	1
Pitch (mm)	.5
Max Height (mm)	1.2
Mechanical Data	Herunterladen

Parameter

Architecture	Current Source
DAC Channels	1
Interface	Parallel CMOS
Interpolation	2x,4x
Operating Temperature Range	-40 to 85 C
Package Group	HTQFP
Package Size: mm2:W x L	48HTQFP: 81 mm2: 9 x 9(HTQFP) PKG
Power Consumption(Typ)	435 mW
Rating	Catalog
Resolution	14 Bits
SFDR	76 dB
Sample / Update Rate	400 MSPS

Öko-Plan

RoHS

Compliant

Design Kits und Evaluierungsmodule

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Anwendungshinweise

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The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
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Q4 2009 Issue Analog Applications Journal
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Wideband Complementary Current Output DAC Single-Ended Interface
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High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
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Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
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This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
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CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
PDF, 424 Kb, Datei veröffentlicht: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

Modellreihe

Serie: DAC5674 (3)

DAC5674IPHP DAC5674IPHPG4 DAC5674IPHPR

Herstellerklassifikation

Semiconductors > Data Converters > Digital-to-Analog Converters (DACs) > High Speed DACs (>10MSPS)