Datasheet Texas Instruments CD74AC74E — Datenblatt
Hersteller | Texas Instruments |
Serie | CD74AC74 |
Artikelnummer | CD74AC74E |
Dual Positive-Edge-Triggered D-Type Flip-Flops mit Set und Reset 14-PDIP -55 auf 125
Datenblätter
CD54AC74, CD74AC74 datasheet
PDF, 786 Kb, Revision: D, Datei veröffentlicht: Dec 5, 2002
Auszug aus dem Dokument
Preise
Status
Lifecycle Status | Active (Recommended for new designs) |
Manufacture's Sample Availability | No |
Verpackung
Pin | 14 |
Package Type | N |
Industry STD Term | PDIP |
JEDEC Code | R-PDIP-T |
Package QTY | 25 |
Carrier | TUBE |
Device Marking | CD74AC74E |
Width (mm) | 6.35 |
Length (mm) | 19.3 |
Thickness (mm) | 3.9 |
Pitch (mm) | 2.54 |
Max Height (mm) | 5.08 |
Mechanical Data | Herunterladen |
Parameter
3-State Output | No |
Bits | 2 |
F @ Nom Voltage(Max) | 100 Mhz |
ICC @ Nom Voltage(Max) | 0.04 mA |
Operating Temperature Range | -55 to 125 C |
Output Drive (IOL/IOH)(Max) | 24/-24 mA |
Package Group | PDIP |
Package Size: mm2:W x L | See datasheet (PDIP) PKG |
Rating | Catalog |
Schmitt Trigger | No |
Technology Family | AC |
VCC(Max) | 5.5 V |
VCC(Min) | 1.5 V |
Voltage(Nom) | 1.5,3.3,5 V |
tpd @ Nom Voltage(Max) | 114,12.7,9.1 ns |
Öko-Plan
RoHS | Compliant |
Pb Free | Yes |
Anwendungshinweise
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, Datei veröffentlicht: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
Modellreihe
Serie: CD74AC74 (8)
Herstellerklassifikation
- Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Flip-Flop