Datasheet Texas Instruments TMS320C6672ACYP25 — Datenblatt

Hersteller	Texas Instruments
Serie	TMS320C6672
Artikelnummer	TMS320C6672ACYP25

Multicore-Fest- und Gleitkomma-Digitalsignalprozessor 841-FCBGA 0 bis 85

Datenblätter

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PDF, 2.1 Mb, Revision: E, Datei veröffentlicht: May 7, 2014

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Preise

Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes

Verpackung

Pin	841	841	841
Package Type	CYP	CYP	CYP
Package QTY	44	44	44
Device Marking	TMS320C6672CYP	@2010 TI	1.25GHZ
Width (mm)	24	24	24
Length (mm)	24	24	24
Thickness (mm)	2.82	2.82	2.82
Mechanical Data	Herunterladen	Herunterladen	Herunterladen

Parameter

Applications	Communications and Telecom
DRAM	DDR3
DSP	2 C66x
DSP MHz	1000,1250,1500 Max.
EMAC	2-Port 1Gb Switch
GFLOPS	32,40,48
On-Chip L2 Cache	1024 KB
Operating Temperature Range	-40 to 100,0 to 85 C
Other On-Chip Memory	4096 KB
PCI/PCIe	2 PCIe Gen2
Package Size: mm2:W x L	See datasheet (FCBGA) PKG
Rating	Catalog
Serial I/O	I2C,RapidIO,SPI,TSIP,UART
Serial RapidIO	1 (four lanes)
Total On-Chip Memory	5376 KB

Öko-Plan

RoHS

Compliant

Design Kits und Evaluierungsmodule

Development Kits: TMDSEVM6678
TMS320C6678 Evaluation Modules
Lifecycle Status: Active (Recommended for new designs)
Daughter Cards: TMDXEVMPCI
AMC to PCIe Adapter Card
Lifecycle Status: Active (Recommended for new designs)
Development Kits: HL5CABLE
Hyperlink Cable
Lifecycle Status: Active (Recommended for new designs)
JTAG Emulators/ Analyzers: TMDSEMU200-U
XDS200 USB Debug Probe
Lifecycle Status: Active (Recommended for new designs)
JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
XDS560v2 System Trace USB & Ethernet Debug Probe
Lifecycle Status: Active (Recommended for new designs)
JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
XDS560v2 System Trace USB Debug Probe
Lifecycle Status: Active (Recommended for new designs)

Anwendungshinweise

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TI Keystone DSP Hyperlink SerDes IBIS-AMI Models
PDF, 3.2 Mb, Datei veröffentlicht: Oct 9, 2014
This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP Hyperlink interface.
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TI Keystone DSP PCIe SerDes IBIS-AMI Models
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This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP PCIe interface.
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SerDes Implementation Guidelines for KeyStone I Devices
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The goal of KeyStone I SerDes collateral material is to make system implementation easier for the customer by providing the system solution. For these SerDes-based interfaces, it is not assumed that the system designer is familiar with the industry specifications, SerDes technology, or RF/microwave PCB design. However, it is still expected that the PCB design work will be supervised by a knowledge
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KeyStone I DDR3 Initialization (Rev. E)
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The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP
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TMS320C66x DSP Generation of Devices (Rev. A)
PDF, 245 Kb, Revision: A, Datei veröffentlicht: Apr 25, 2011
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Hardware Design Guide for KeyStone Devices (Rev. C)
PDF, 1.7 Mb, Revision: C, Datei veröffentlicht: Sep 15, 2013
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SERDES Link Commissioning on KeyStone I and II Devices
PDF, 138 Kb, Datei veröffentlicht: Apr 13, 2016
The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.
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PCIe Use Cases for KeyStone Devices
PDF, 320 Kb, Datei veröffentlicht: Dec 13, 2011
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Clocking Design Guide for KeyStone Devices
PDF, 1.5 Mb, Datei veröffentlicht: Nov 9, 2010
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The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)
PDF, 20 Kb, Revision: A, Datei veröffentlicht: Nov 10, 2010
The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: вЂњint gvar;вЂќ gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
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Optimizing Loops on the C66x DSP
PDF, 585 Kb, Datei veröffentlicht: Nov 9, 2010
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DDR3 Design Requirements for KeyStone Devices (Rev. B)
PDF, 582 Kb, Revision: B, Datei veröffentlicht: Jun 5, 2014
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Multicore Programming Guide (Rev. B)
PDF, 1.8 Mb, Revision: B, Datei veröffentlicht: Aug 29, 2012
As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore

Modellreihe

Serie: TMS320C6672 (4)

TMS320C6672ACYP TMS320C6672ACYP25 TMS320C6672ACYPA TMS320C6672ACYPA25

Herstellerklassifikation

Semiconductors > Processors > Digital Signal Processors > C6000 DSP > C66x DSP