Datasheet Texas Instruments 74ACT11000NSRE4 — Datenblatt
| Hersteller | Texas Instruments |
| Serie | 74ACT11000 |
| Artikelnummer | 74ACT11000NSRE4 |
Vierfache Positiv-NAND-Gatter mit 2 Eingängen 16-SO -40 bis 85
Datenblätter
Quadruple 2-Input Positive-NAND Gates datasheet
PDF, 384 Kb, Revision: A, Datei veröffentlicht: Apr 1, 1993
Auszug aus dem Dokument
Preise
Status
| Lifecycle Status | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No |
Verpackung
| Pin | 16 |
| Package Type | NS |
| Industry STD Term | SOP |
| JEDEC Code | R-PDSO-G |
| Width (mm) | 5.3 |
| Length (mm) | 10.3 |
| Thickness (mm) | 1.95 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 2 |
| Mechanical Data | Herunterladen |
Parameter
| Approx. Price (US$) | 0.88 | 1ku |
| Bits(#) | 4 |
| F @ Nom Voltage(Max)(Mhz) | 90 |
| ICC @ Nom Voltage(Max)(mA) | 0.04 |
| Input Type | TTL |
| Operating Temperature Range(C) | -40 to 85 |
| Output Drive (IOL/IOH)(Max)(mA) | 24/-24 |
| Output Type | CMOS |
| Package Group | PDIP SOIC |
| Package Size: mm2:W x L (PKG) | See datasheet (PDIP) |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | ACT |
| VCC(Max)(V) | 5.5 |
| VCC(Min)(V) | 4.5 |
| Voltage(Nom)(V) | 5 |
| tpd @ Nom Voltage(Max)(ns) | 12.3 |
Öko-Plan
| RoHS | Not Compliant |
| Pb Free | No |
Anwendungshinweise
- Selecting the Right Level Translation Solution (Rev. A)PDF, 313 Kb, Revision: A, Datei veröffentlicht: Jun 22, 2004
Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati - Introduction to LogicPDF, 93 Kb, Datei veröffentlicht: Apr 30, 2015
- Shelf-Life Evaluation of Lead-Free Component FinishesPDF, 1.3 Mb, Datei veröffentlicht: May 24, 2004
The integrated circuit (IC) industry is converting to lead (Pb)-free termination finishes for leadframe-based packages. IC component users need to know the maximum length of time that components can be stored prior to being soldered. This study predicts shelf life of the primary Pb-free finishes being proposed by the industry. Components were exposed to a controlled environment, with known aging a - Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)PDF, 614 Kb, Revision: C, Datei veröffentlicht: Dec 2, 2015
- Semiconductor Packing Material Electrostatic Discharge (ESD) ProtectionPDF, 337 Kb, Datei veröffentlicht: Jul 8, 2004
Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge - CMOS Power Consumption and CPD Calculation (Rev. B)PDF, 89 Kb, Revision: B, Datei veröffentlicht: Jun 1, 1997
Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale - TI IBIS File Creation Validation and Distribution ProcessesPDF, 380 Kb, Datei veröffentlicht: Aug 29, 2002
The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con - Implications of Slow or Floating CMOS Inputs (Rev. D)PDF, 260 Kb, Revision: D, Datei veröffentlicht: Jun 23, 2016
- Designing With Logic (Rev. C)PDF, 186 Kb, Revision: C, Datei veröffentlicht: Jun 1, 1997
Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w - Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, Datei veröffentlicht: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
Modellreihe
Serie: 74ACT11000 (9)
Herstellerklassifikation
- Semiconductors > Logic > Gate > NAND Gate