Datasheet Texas Instruments CLVTH162244IDGGREP — Datenblatt

Hersteller	Texas Instruments
Serie	SN74LVTH162244-EP
Artikelnummer	CLVTH162244IDGGREP

Erweitertes Produkt 3.3.-V Abt 16-Bit-Puffer / Treiber mit 3-Zustands-Ausgängen 48-TSSOP -40 bis 85

Datenblätter

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PDF, 292 Kb, Datei veröffentlicht: Nov 10, 2003

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Preise

Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Verpackung

Pin	48
Package Type	DGG
Industry STD Term	TSSOP
JEDEC Code	R-PDSO-G
Package QTY	2000
Carrier	LARGE T&R
Device Marking	LH162244EP
Width (mm)	6.1
Length (mm)	12.5
Thickness (mm)	1.15
Pitch (mm)	.5
Max Height (mm)	1.2
Mechanical Data	Herunterladen

Parameter

Bits	16
Input Type	TTL/CMOS
Operating Temperature Range	-40 to 85 C
Output Type	LVTTL
Package Group	TSSOP
Package Size: mm2:W x L	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) PKG
Rating	HiRel Enhanced Product
Schmitt Trigger	No
Technology Family	LVT
VCC(Max)	3.6 V
VCC(Min)	2.7 V
Voltage(Nom)	3.3 V

Öko-Plan

RoHS

Compliant

Anwendungshinweise

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LVT Family Characteristics (Rev. A)
PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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LVT-to-LVTH Conversion
PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
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16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
PDF, 895 Kb, Revision: B, Datei veröffentlicht: May 22, 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
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Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
PDF, 105 Kb, Revision: A, Datei veröffentlicht: Aug 1, 1997
The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
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Understanding Advanced Bus-Interface Products Design Guide
PDF, 253 Kb, Datei veröffentlicht: May 1, 1996
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Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
PDF, 209 Kb, Datei veröffentlicht: May 10, 2002
Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

Modellreihe

Serie: SN74LVTH162244-EP (2)

CLVTH162244IDGGREP V62/04708-01XE

Herstellerklassifikation

Semiconductors > Space & High Reliability > Logic Products > Buffers/Drivers/Transceivers > Buffer Drivers