Datasheet Texas Instruments CDC7005ZVA — Datenblatt
| Hersteller | Texas Instruments |
| Serie | CDC7005 |
| Artikelnummer | CDC7005ZVA |
Hochleistungs-Synchronisierer mit geringem Phasenrauschen und geringem Schräglauf, der den Ref-Takt mit VCXO 64-BGA -40 bis 85 synchronisiert
Datenblätter
3.3-V High Performance Clock Synthesizer & Jitter Cleaner datasheet
PDF, 1.1 Mb, Revision: L, Datei veröffentlicht: Jun 4, 2009
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Preise
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Verpackung
| Pin | 64 |
| Package Type | ZVA |
| Industry STD Term | BGA |
| JEDEC Code | S-PBGA-N |
| Package QTY | 348 |
| Carrier | JEDEC TRAY (10+1) |
| Device Marking | CK7005Z |
| Width (mm) | 8 |
| Length (mm) | 8 |
| Thickness (mm) | .96 |
| Pitch (mm) | .8 |
| Max Height (mm) | 1.4 |
| Mechanical Data | Herunterladen |
Parameter
| Divider Ratio | 1 to 16 |
| Input Level | LVCMOS (REF_CLK),LVPECL (VCXO_CLK) |
| Number of Inputs | 1 |
| Number of Outputs | 5 |
| Operating Temperature Range | -40 to 85 C |
| Output Frequency(Max) | 800 MHz |
| Output Frequency(Min) | 10 MHz |
| Output Level | LVPECL |
| Package Group | BGA |
| Package Size: mm2:W x L | 64BGA: 64 mm2: 8 x 8(BGA) PKG |
| Rating | Catalog |
| Special Features | OPAMP for Active Loop Filter,Programmable Delay |
| Supply Voltage(Max) | 3.6 V |
| Supply Voltage(Min) | 3 V |
Öko-Plan
| RoHS | Compliant |
| Pb Free | Yes |
Design Kits und Evaluierungsmodule
- Evaluation Modules & Boards: CDC7005QFN-EVM
CDC7005 QFN Package Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: CDC7005-EVM
CDC7005 Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: CDCM7005BGA-EVM
CDCM7005 BGA Package Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: CDCM7005QFN-EVM
CDCM7005 QFN Package Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Anwendungshinweise
- Open Loop Phase-Noise Performance of CDC7005 at Various FrequenciesPDF, 353 Kb, Datei veröffentlicht: Dec 17, 2004
This application brief presents phase-noise data taken on Texas Instruments CDC7005 jitter cleaner and synchronizer PLL. The phase noise performance of CDC7005 depends on thephase noise of the reference clock, the voltage-controlled crystal oscillator (VCXO) clock,and the CDC7005 itself. This applications brief shows the phase noise performance of the CDC7005 clock synthesizer at the most popula - Phase Noise (Jitter) Performance of CDC7005 With Different VCXOs (Rev. A)PDF, 1.3 Mb, Revision: A, Datei veröffentlicht: Jul 19, 2005
- Using The CDC7005 as a 1:5 PECL Buffer w/Programmable Divider Ratio (Rev. B)PDF, 85 Kb, Revision: B, Datei veröffentlicht: Dec 15, 2009
- General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner (Rev. A)PDF, 207 Kb, Revision: A, Datei veröffentlicht: Dec 16, 2003
- Basics of the CDC7005 Hold FunctionPDF, 233 Kb, Datei veröffentlicht: Apr 13, 2006
The CDC7005 is a high-performance clock synthesizer and jitter cleaner with implemented hold functionality. The hold functionality can be used for fail-safe operation if the reference clock is missing. This application report describes the basis, the advantages, and the limitations of the CDC7005 hold functionality. Additionally, a discrete realization of a simplified external hold function is sho - Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC DevPDF, 627 Kb, Datei veröffentlicht: Jun 25, 2004
Texas Instruments has introduced a family of devices suited to meet the demand for high-speed, high-IF sampling ADC devices like the ADS5500 ADC, capable of sampling at 125 MSPS. To realize the full potential of these high performance devices, it is imperative to provide an extremely low phase noise clock source. The CDC7005 clock distribution chip offers a real-world clocking solution to meet the
Modellreihe
Serie: CDC7005 (8)
Herstellerklassifikation
- Semiconductors > Clock and Timing > Clock Jitter Cleaners > Single-Loop PLL