Datasheet Texas Instruments ADS7263SRHBT — Datenblatt

Hersteller	Texas Instruments
Serie	ADS7263
Artikelnummer	ADS7263SRHBT

14-Bit 1MSPS 4x2 / 2x2 Simultane Abtastung SAR ADC 32-VQFN -40 bis 125

Datenblätter

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PDF, 1.4 Mb, Revision: D, Datei veröffentlicht: Sep 2, 2017

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Preise

Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes

Verpackung

Pin	32	32
Package Type	RHB	RHB
Industry STD Term	VQFN	VQFN
JEDEC Code	S-PQFP-N	S-PQFP-N
Package QTY	250	250
Carrier	SMALL T&R	SMALL T&R
Device Marking	7263	ADS
Width (mm)	5	5
Length (mm)	5	5
Thickness (mm)	.9	.9
Pitch (mm)	.5	.5
Max Height (mm)	1	1
Mechanical Data	Herunterladen	Herunterladen

Parameter

# Input Channels	4
Analog Voltage AVDD(Max)	5.5 V
Analog Voltage AVDD(Min)	2.7 V
Architecture	SAR
Digital Supply(Max)	5.5 V
Digital Supply(Min)	2.3 V
INL(Max)	2 +/-LSB
Input Range(Max)	5.5 V
Input Type	Differential,Pseudo-Differential
Integrated Features	N/A
Interface	SPI
Multi-Channel Configuration	Multiplexed,Simultaneous Sampling
Operating Temperature Range	-40 to 125 C
Package Group	VQFN
Package Size: mm2:W x L	32VQFN: 25 mm2: 5 x 5(VQFN) PKG
Power Consumption(Typ)	47.2 mW
Rating	Catalog
Reference Mode	Ext,Int
Resolution	14 Bits
SINAD	84 dB
SNR	85 dB
Sample Rate (max)	1MSPS SPS
Sample Rate(Max)	1 MSPS
THD(Typ)	-92 dB

Öko-Plan

RoHS

Compliant

Design Kits und Evaluierungsmodule

Evaluation Modules & Boards: ADS8363EVM
ADS8363 Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
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Anwendungshinweise

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Using the Sequencer and Pseudo-Differential Features of the ADS8363
PDF, 161 Kb, Datei veröffentlicht: May 21, 2014
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Interfacing to the ADS8363 Pseudo-Differential Operating Mode
PDF, 548 Kb, Datei veröffentlicht: Aug 4, 2014
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Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
PDF, 227 Kb, Revision: A, Datei veröffentlicht: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
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Determining Minimum Acquisition Times for SAR ADCs, part 2
PDF, 215 Kb, Datei veröffentlicht: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
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Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
PDF, 69 Kb, Revision: A, Datei veröffentlicht: May 18, 2015
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A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
PDF, 425 Kb, Revision: B, Datei veröffentlicht: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
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Principles of Data Acquisition and Conversion (Rev. A)
PDF, 132 Kb, Revision: A, Datei veröffentlicht: Apr 16, 2015

Modellreihe

Serie: ADS7263 (2)

ADS7263SRHBR ADS7263SRHBT

Herstellerklassifikation

Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)