Datasheet Texas Instruments ADS8381IBPFBT — Datenblatt
| Hersteller | Texas Instruments |
| Serie | ADS8381 |
| Artikelnummer | ADS8381IBPFBT |
18 Bit 580KSPS parallel ADC 48-TQFP -40 bis 85
Datenblätter
18-Bit, 580kHz, Unipolar Input, Micro Power Sampling Analog-to-Digital Converter datasheet
PDF, 1.0 Mb, Revision: D, Datei veröffentlicht: Feb 9, 2005
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Preise
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Verpackung
| Pin | 48 | 48 |
| Package Type | PFB | PFB |
| Industry STD Term | TQFP | TQFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G |
| Package QTY | 250 | 250 |
| Carrier | SMALL T&R | SMALL T&R |
| Device Marking | ADS8381I | B |
| Width (mm) | 7 | 7 |
| Length (mm) | 7 | 7 |
| Thickness (mm) | 1 | 1 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | Herunterladen | Herunterladen |
Parameter
| # Input Channels | 1 |
| Analog Voltage AVDD(Max) | 5.25 V |
| Analog Voltage AVDD(Min) | 4.75 V |
| Architecture | SAR |
| Digital Supply(Max) | 5.25 V |
| Digital Supply(Min) | 2.7 V |
| INL(Max) | 4 +/-LSB |
| Input Range(Max) | 4.2 V |
| Input Type | Pseudo-Differential,Single-Ended |
| Integrated Features | Oscillator |
| Interface | Parallel |
| Multi-Channel Configuration | N/A |
| Operating Temperature Range | -40 to 85 C |
| Package Group | TQFP |
| Package Size: mm2:W x L | 48TQFP: 81 mm2: 9 x 9(TQFP) PKG |
| Power Consumption(Typ) | 115 mW |
| Rating | Catalog |
| Reference Mode | Ext |
| Resolution | 18 Bits |
| SINAD | 88 dB |
| SNR | 88 dB |
| Sample Rate (max) | 580kSPS SPS |
| Sample Rate(Max) | 0.58 MSPS |
| THD(Typ) | -112 dB |
Öko-Plan
| RoHS | Compliant |
Design Kits und Evaluierungsmodule
- Evaluation Modules & Boards: ADS8381EVM
ADS8381 Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Anwendungshinweise
- Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)PDF, 227 Kb, Revision: A, Datei veröffentlicht: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different - Determining Minimum Acquisition Times for SAR ADCs, part 2PDF, 215 Kb, Datei veröffentlicht: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
Modellreihe
Serie: ADS8381 (2)
- ADS8381IBPFBT ADS8381IPFBT
Herstellerklassifikation
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)