Datasheet Texas Instruments CDC7005RGZTG4 — Datenblatt

Hersteller	Texas Instruments
Serie	CDC7005
Artikelnummer	CDC7005RGZTG4

Hochleistungs-Synchronisierer mit geringem Phasenrauschen und geringem Schräglauf, der den Ref-Takt mit VCXO 48-VQFN -40 bis 85 synchronisiert

Datenblätter

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PDF, 1.1 Mb, Revision: L, Datei veröffentlicht: Jun 4, 2009

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Preise

Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes

Verpackung

Pin	48
Package Type	RGZ
Industry STD Term	VQFN
JEDEC Code	S-PQFP-N
Package QTY	250
Carrier	SMALL T&R
Device Marking	CDC7005
Width (mm)	7
Length (mm)	7
Thickness (mm)	.9
Pitch (mm)	.5
Max Height (mm)	1
Mechanical Data	Herunterladen

Parameter

Divider Ratio	1 to 16
Input Level	LVCMOS (REF_CLK),LVPECL (VCXO_CLK)
Number of Inputs	1
Number of Outputs	5
Operating Temperature Range	-40 to 85 C
Output Frequency(Max)	800 MHz
Output Frequency(Min)	10 MHz
Output Level	LVPECL
Package Group	VQFN
Package Size: mm2:W x L	48VQFN: 49 mm2: 7 x 7(VQFN) PKG
Rating	Catalog
Special Features	OPAMP for Active Loop Filter,Programmable Delay
Supply Voltage(Max)	3.6 V
Supply Voltage(Min)	3 V

Öko-Plan

RoHS

Compliant

Design Kits und Evaluierungsmodule

Evaluation Modules & Boards: CDC7005QFN-EVM
CDC7005 QFN Package Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Evaluation Modules & Boards: CDC7005-EVM
CDC7005 Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
- Herunterladen
Evaluation Modules & Boards: CDCM7005BGA-EVM
CDCM7005 BGA Package Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Evaluation Modules & Boards: CDCM7005QFN-EVM
CDCM7005 QFN Package Evaluation Module
Lifecycle Status: Active (Recommended for new designs)

Anwendungshinweise

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Open Loop Phase-Noise Performance of CDC7005 at Various Frequencies
PDF, 353 Kb, Datei veröffentlicht: Dec 17, 2004
This application brief presents phase-noise data taken on Texas Instruments CDC7005 jitter cleaner and synchronizer PLL. The phase noise performance of CDC7005 depends on thephase noise of the reference clock, the voltage-controlled crystal oscillator (VCXO) clock,and the CDC7005 itself. This applications brief shows the phase noise performance of the CDC7005 clock synthesizer at the most popula
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Phase Noise (Jitter) Performance of CDC7005 With Different VCXOs (Rev. A)
PDF, 1.3 Mb, Revision: A, Datei veröffentlicht: Jul 19, 2005
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Using The CDC7005 as a 1:5 PECL Buffer w/Programmable Divider Ratio (Rev. B)
PDF, 85 Kb, Revision: B, Datei veröffentlicht: Dec 15, 2009
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General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner (Rev. A)
PDF, 207 Kb, Revision: A, Datei veröffentlicht: Dec 16, 2003
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Basics of the CDC7005 Hold Function
PDF, 233 Kb, Datei veröffentlicht: Apr 13, 2006
The CDC7005 is a high-performance clock synthesizer and jitter cleaner with implemented hold functionality. The hold functionality can be used for fail-safe operation if the reference clock is missing. This application report describes the basis, the advantages, and the limitations of the CDC7005 hold functionality. Additionally, a discrete realization of a simplified external hold function is sho
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Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev
PDF, 627 Kb, Datei veröffentlicht: Jun 25, 2004
Texas Instruments has introduced a family of devices suited to meet the demand for high-speed, high-IF sampling ADC devices like the ADS5500 ADC, capable of sampling at 125 MSPS. To realize the full potential of these high performance devices, it is imperative to provide an extremely low phase noise clock source. The CDC7005 clock distribution chip offers a real-world clocking solution to meet the

Modellreihe

Serie: CDC7005 (8)

CDC7005RGZ CDC7005RGZR CDC7005RGZRG4 CDC7005RGZT CDC7005RGZTG4 CDC7005ZVA CDC7005ZVAR CDC7005ZVAT

Herstellerklassifikation

Semiconductors > Clock and Timing > Clock Jitter Cleaners > Single-Loop PLL