Datasheet Texas Instruments SN74ALVC245PWR — Datenblatt

Hersteller	Texas Instruments
Serie	SN74ALVC245
Artikelnummer	SN74ALVC245PWR

Oktalbus-Transceiver mit 3-Zustands-Ausgängen 20-TSSOP -40 bis 85

Datenblätter

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PDF, 1.3 Mb, Revision: D, Datei veröffentlicht: Jul 27, 2004

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Preise

Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Verpackung

Pin	20
Package Type	PW
Industry STD Term	TSSOP
JEDEC Code	R-PDSO-G
Package QTY	2000
Carrier	LARGE T&R
Device Marking	VA245
Width (mm)	4.4
Length (mm)	6.5
Thickness (mm)	1
Pitch (mm)	.65
Max Height (mm)	1.2
Mechanical Data	Herunterladen

Parameter

Bits	8
F @ Nom Voltage(Max)	100 Mhz
ICC @ Nom Voltage(Max)	0.01 mA
Operating Temperature Range	-40 to 85 C
Output Drive (IOL/IOH)(Max)	-24/24 mA
Package Group	TSSOP
Package Size: mm2:W x L	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) PKG
Rating	Catalog
Schmitt Trigger	No
Technology Family	ALVC
VCC(Max)	3.6 V
VCC(Min)	1.65 V
Voltage(Nom)	1.8,2.5,2.7,3.3 V
tpd @ Nom Voltage(Max)	3.4,5.5 ns

Öko-Plan

RoHS

Compliant

Anwendungshinweise

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TI SN74ALVC16835 Component Specification Analysis for PC100
PDF, 43 Kb, Datei veröffentlicht: Aug 3, 1998
The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
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Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
PDF, 96 Kb, Revision: A, Datei veröffentlicht: May 13, 1998
Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
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16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
PDF, 895 Kb, Revision: B, Datei veröffentlicht: May 22, 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
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Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
PDF, 154 Kb, Revision: A, Datei veröffentlicht: Sep 8, 1999
In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families
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Understanding Advanced Bus-Interface Products Design Guide
PDF, 253 Kb, Datei veröffentlicht: May 1, 1996

Modellreihe

Serie: SN74ALVC245 (11)

SN74ALVC245DGVR SN74ALVC245DW SN74ALVC245DWR SN74ALVC245NSR SN74ALVC245PW SN74ALVC245PWG4 SN74ALVC245PWR SN74ALVC245PWRE4 SN74ALVC245PWRG4 SN74ALVC245RGYR SN74ALVC245RGYRG4

Herstellerklassifikation

Semiconductors > Logic > Buffer/Driver/Transceiver > Standard Transceiver