Datasheet Texas Instruments TMS320C6472EZTZA6 — Datenblatt

Hersteller	Texas Instruments
Serie	TMS320C6472
Artikelnummer	TMS320C6472EZTZA6

Datenblätter

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Öko-Plan

Design Kits und Evaluierungsmodule

• Development Kits: TMDSEVM6472
  TMS320C6472 Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
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• JTAG Emulators/ Analyzers: TMDSEMU200-U
  XDS200 USB Debug Probe
  Lifecycle Status: Active (Recommended for new designs)
  
• JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
  XDS560v2 System Trace USB & Ethernet Debug Probe
  Lifecycle Status: Active (Recommended for new designs)
  
• JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
  XDS560v2 System Trace USB Debug Probe
  Lifecycle Status: Active (Recommended for new designs)
  

Anwendungshinweise

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  TMS320C6472/TMS320TCI6486 DDR2 Implementation Guidelines (Rev. E)
  PDF, 196 Kb, Revision: E, Datei veröffentlicht: Aug 1, 2012
  This application report contains implementation instructions for the DDR2 interface contained on the TMS320C6472/TMS320TCI6486 DSP devices. The approach to specifying interface timing for the DDR2 interface is quite different than on previous devices.The previous approach specified device timing in terms of data sheet specifications and simulation models. The customer was required to obtain c
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  EMAC Implementation Guide for the TMS320C6472/TMS320TCI6486 (Rev. A)
  PDF, 982 Kb, Revision: A, Datei veröffentlicht: Oct 29, 2009
  The TMS320TCI6486/TMS320C6472 device contains two independent Ethernet MAC modules, EMAC0 and EMAC1, and a shared MDIO controller. This document describes system implementation details of the EMAC and MDIO modules on TCI6486/C6472 device. For a detailed functional description of the EMAC/MDIO modules such as architecture and operation as well as register definitions, see the TMS320C6472/TMS32
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  Power-On Self Test for the TMS320C6472/TMS320TCI6486 (Rev. A)
  PDF, 118 Kb, Revision: A, Datei veröffentlicht: Oct 29, 2009
  This Power-On Self Test (POST) is designed to verify the operation of the TMS320TCI6486/TMS320C6472. Ten modules are included in this test: Chk6xTest, MemoryEdmaTest, TimerTest, TsipTest, I2cTest, SrioTest, EmacTest, MdioTest, and MultigemTest. These modules check the proper operation of the CPU cores, internal memory, cache operations, and several on-chip peripherals: EDMA3, Timers, TSIP, PLLs, S
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  TMS320C6472 Fixed-Point Digital Signal Processor Technical Brief (Rev. B)
  PDF, 137 Kb, Revision: B, Datei veröffentlicht: Jul 1, 2011
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  Throughput Application Report for the TMS320C6472/TMS320TCI6486 (Rev. A)
  PDF, 403 Kb, Revision: A, Datei veröffentlicht: Oct 29, 2009
  The TMS320C6472/TMS320TCI6486 has six C64x+ Megamodule cores that run at 500 MHz, 625 MHz, or 700 MHz. This document has been written based on the performance of the C6472/TCI6486 device running at 500 MHz and 625 MHz. Each megamodule has 32KB of L1D SRAM, 32KB of L1P SRAM, and 608KB of LL2 SRAM and all six cores share 768KB of SL2 SRAM. A 32-bit 533-MHz DDR2 SDRAM interface is provided on the DSP
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  Using Advanced Event Triggering to Debug Real-Time Problems in Embedded Systems
  PDF, 919 Kb, Datei veröffentlicht: May 17, 2002
  As more and more system components become embedded within the system processor chip, new techniques are required for debug. Signals and busses that were historically available for probe connection at external package pins, are now hidden from the users within the processor package. This problem is referred to as vanishing visibility meaning that the user can no longer employ traditional techniques
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  Serial RapidIO Implementation Guidelines for the TMS320C6472/TMS320TCI6486 (Rev. A)
  PDF, 73 Kb, Revision: A, Datei veröffentlicht: Oct 29, 2009
  This application report contains implementation instructions for the Serial RapidIOВ® (SRIO) interface on the TMS320TCI6486/TMS320C6472 DSP device. The approach to specifying interface timing and physical requirements for the SRIO interface is quite different than previous approaches for other interfaces.Serial RapidIO is an industry-standard, high-speed, switched-packet interconnect. Phys
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  Hardware Design Guide for the TMS320C6472/TMS320TCI6486 (Rev. B)
  PDF, 322 Kb, Revision: B, Datei veröffentlicht: Oct 26, 2009
  This application report describes system design considerations for the TMS320C6472/TMS320TCI6486 (C6472/TCI6486) Digital Signal Processor (DSP). The objective of this document is to simplify the design of the C6472/TCI6486 device into a system/board design. In some cases, there is information overlapping with the TMS320TCI6486 Communications Infrastructure data manual (
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  TMS320C6472 Power Consumption Summary (Rev. A)
  PDF, 58 Kb, Revision: A, Datei veröffentlicht: Sep 17, 2010
  This document discusses the power consumption of the Texas Instruments TMS320C6472 digital signal processor (DSP). The power consumption on the TMS320C6472 device is highly application-dependent; therefore, a power spreadsheet that estimates power consumption is provided along with this application report. This spreadsheet can be used to model power consumption for user applications such as pow
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  EDMA v3.0 (EDMA3) Migration Guide for TMS320TCI648x DSP
  PDF, 345 Kb, Datei veröffentlicht: Dec 23, 2005
  The TMS320TCI648x devices introduce a newly designed Enhanced Direct Memory Access (EDMA3). The EDMA3 has many new features that improve system performance and enhance debugging capabilities. This document summarizes the key differences between EDMA3 on the TMS320TCI648x devices and EDMA2 on the TMS320C64x devices. This document also provides guidance for migrating from EDMA2 to EDMA3.
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  TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers
  PDF, 452 Kb, Datei veröffentlicht: Mar 26, 2010
  This reference design is intended for designers who wish to design up to eight TMS320C6472 Digital Signal Processors into a system using a nominal input voltage of 5 V, with a flexible design using external FETs, and low-dropout regulators for the low-power rails.
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  Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472)
  PDF, 251 Kb, Datei veröffentlicht: Mar 31, 2010
  This reference design is intended for designers who wish to design a TMS320C6472 Digital Signal Processor into a system using a nominal input voltage of 5 V, DC/DC converters with integrated FETs, and allowing for ease-of-design and a smaller solution size.
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  'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472)
  PDF, 441 Kb, Datei veröffentlicht: Mar 26, 2010
  This reference design is intended for designers who wish to design up to eight TMS320C6472 Digital Signal Processors into a system using a nominal input voltage of 12 V, external FETs for design flexibility, and low-dropout regulators for the low-power rails.
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  Power Ref Design for TMS320C6472, 12-Vin Digital Pwr Cntrlrs, and LDOs (Rev. A)
  PDF, 559 Kb, Revision: A, Datei veröffentlicht: May 24, 2010
  This design was created to help those wanting to design a TMS320C6472 digital signal processor into a system using a nominal input of 12 V, having a highly flexible power design, and the ability to monitor temperature as well as dynamically monitoring and controlling voltage and current.
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  Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs
  PDF, 558 Kb, Datei veröffentlicht: Apr 28, 2010
  This design was created to help designers wishing to design up to eight TMS320C6472 Digital Signal Processors into a system using a nominal input voltage of 12 V, having a highly flexible power design, the ability to monitor temperature, and dynamically monitor and control voltage and current.
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  Power Reference Design for the 'C6472 12V DCDC Controllers and LDOs
  PDF, 245 Kb, Datei veröffentlicht: Mar 26, 2010
  This reference design is intended for designers who wish to design a TMS320C6472 Digital Signal Processor into a system using a nominal input voltage of 12 V external FETs for design flexibility and low-dropout regulators for the low-power rails.
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  Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A)
  PDF, 80 Kb, Revision: A, Datei veröffentlicht: Jul 19, 2013
  This application report describes the error detection and correction mechanism of the C64x+/C674x megamodule L1P and L2 memories implemented on some devices. Depending on the type of application, these mechanisms are used to either provide diagnostic measures to detect faults in the memory that could lead to unacceptable risk for the user or to increase the availability of the system.
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  Multicore Programming Guide (Rev. B)
  PDF, 1.8 Mb, Revision: B, Datei veröffentlicht: Aug 29, 2012
  As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
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  Using IBIS Models for Timing Analysis (Rev. A)
  PDF, 301 Kb, Revision: A, Datei veröffentlicht: Apr 15, 2003
  Today?s high-speed interfaces require strict timings and accurate system design. To achieve the necessary timings for a given system, input/output buffer information specification (IBIS) models must be used. These models accurately represent the device drivers under various process conditions. Board characteristics, such as impedance, loading, length, number of nodes, etc., affect how the device d
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  TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A)
  PDF, 310 Kb, Revision: A, Datei veröffentlicht: Oct 20, 2005
  This document describes migration from the Texas Instruments TMS320C64xв„ў digital signal processor (DSP) to the TMS320C64x+в„ў DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Functionality in the devices that is identical is not included. For detailed information about either device, see the TMS320C64x/C64x+ DSP
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  Introduction to TMS320C6000 DSP Optimization
  PDF, 535 Kb, Datei veröffentlicht: Oct 6, 2011
  The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However to fully leverage the architectural features that C6000™ processors offer code optimization may be required. First this document reviews five key concepts in understanding the C6000 DSP architecture and optimization. Then

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• Semiconductors > Processors > Digital Signal Processors > C6000 DSP > Other C6000 DSP