PRELIMINARY EZ-PDTM CCG2 Datasheet USB Type-C Cable Controller
General Description
EZ-PDTM CCG2 is a USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG2 provides a complete USB Type-C and USB Power Delivery port control solution for active cables and powered accessories. It can also be used in many upstream and downstream facing port applications. EZ-PD CCG2 uses Cypress's proprietary M0S8 technology with a 32-bit, 48-MHz ARM® Cortex®-M0 processor with 32-KB flash and integrates a complete Type-C Transceiver including the RP, RD and RA resistors. Applications
USB Type-C EMCA cables USB Type-C Powered Accessories USB Type-C Upstream Facing Ports USB Type-C Downstream Facing Ports Type-C Support Integrated transceiver (baseband PHY) Integrated UFP (RD), and EMCA (RA) termination resistors, and current sources for DFP (RP) Supports one USB Type-C port 2.7-V to 5.5-V operation Two independent VCONN rails with integrated isolation between the two Independent supply voltage pin for GPIO allows 1.71-V to 5.5-V signaling on the I/Os Reset: 1.0 µA, Deep Sleep: 2.5 µA, Sleep: 2.0 mA ± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based on IEC61000-4-2 level 4C 1.63 mm Ч 2.03 mm, 20-ball wafer-level CSP (WLCSP) with 0.4-mm ball pitch 2.5 mm Ч 3.5 mm Ч 0.6 mm 14-pin DFN Supports Industrial Temperature Range (-40 °C to +85 °C) Features
32-bit MCU Subsystem
48-MHz ARM Cortex-M0 CPU 32-KB Flash 4-KB SRAM In-system re-programmable Low-Power Operation Integrated Digital Blocks
Integrated timers and counters to meet response times required by the USB-PD protocol Run-time reconfigurable serial communication block (SCB) with re-configurable I2C, SPI, or UART functionality System-Level ESD on CC and VCONN Pins Packages Clocks and Oscillators Integrated oscillator eliminating the need for external clock Logic Block Diagram
CCG2: USB Type-C Cable Controller
MCU Subsystem Integrated Digital Blocks TCPWM1 SCB2 (I2C, SPI, UART) Advanced High-Performance Bus (AHB) SCB2 (I2C, SPI, UART) Programmable I/O Matrix VCONN1 I/O Subsystem CC5 CORTEX-M0 VCONN2
VDDIO GPIO6 Port 48 MHz Profiles and Configurations Baseband MAC Baseband PHY Integrated RD3, RA4 Flash (32KB) SRAM (4KB) Serial Wire Debug 1 Timer, 2 3 counter, pulse-width modulation block Serial communication block configurable as UART, SPI or I2C Termination resistor read as a UFP 4 Termination resistor read as an EMCA 5 Configuration Channel 6 General-purpose input/output Errata: For information on silicon errata, see "Errata" on page 24. Details include trigger conditions, devices af …